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CDCM61002RHBT PDF预览

CDCM61002RHBT

更新时间： 2024-09-08 06:47:07
品牌 Logo 应用领域
德州仪器 - TI 时钟驱动器时钟发生器逻辑集成电路PC
页数 文件大小 规格书
34页 844K
描述
Two Output, Integrated VCO, Low-Jitter Clock Generator

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CDCM61002RHBT 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFN
包装说明：QFN-32针数：32
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：1.26Samacsys Confidence：
Samacsys Status：ReleasedSamacsys PartID：232423
Samacsys Pin Count：33Samacsys Part Category：Integrated Circuit
Samacsys Package Category：OtherSamacsys Footprint Name：QFN50P500X500X100-33N
Samacsys Released Date：2017-01-12 12:59:53Is Samacsys：N
系列：61002输入调节：MUX
JESD-30 代码：S-PQCC-N32JESD-609代码：e4
长度：5 mm负载电容（CL）：5 pF
逻辑集成电路类型：PLL BASED CLOCK DRIVER湿度敏感等级：2
功能数量：1反相输出次数：
端子数量：32实输出次数：2
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：HVQCCN
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
包装方法：TR峰值回流温度（摄氏度）：260
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.05 ns
座面最大高度：1 mm子类别：Clock Driver
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：5 mm最小 fmax：683.264 MHz
Base Number Matches：1

CDCM61002RHBT 数据手册

 浏览型号CDCM61002RHBT的Datasheet PDF文件第2页浏览型号CDCM61002RHBT的Datasheet PDF文件第3页浏览型号CDCM61002RHBT的Datasheet PDF文件第4页浏览型号CDCM61002RHBT的Datasheet PDF文件第5页浏览型号CDCM61002RHBT的Datasheet PDF文件第6页浏览型号CDCM61002RHBT的Datasheet PDF文件第7页 
CDCM61002  
www.ti.com.................................................................................................................................................... SCAS870B–FEBRUARY 2009–REVISED JULY 2009  
Two Output, Integrated VCO, Low-Jitter Clock Generator  
1
FEATURES  
•
•
•
•
•
Chip Enable Control Pin Available  
2
•
One Single-Ended/Crystal Reference Input  
Including 24.8832 MHz, 25 MHz, and  
26.5625 MHz  
3.3-V Core and I/O Power Supply  
Industrial Temperature Range: –40°C to +85°C  
5-mm × 5-mm, 32-pin, QFN (RHB) Package  
ESD Protection Exceeds 2 kV (HBM)  
•
•
•
Input Frequency Range: 21.875 MHz to  
28.47 MHz  
On-Chip VCO Operates in Frequency Range of  
1.75 GHz to 2.05 GHz  
APPLICATIONS  
•
Low Jitter Clock Driver for High-End Datacom  
Applications Including SONET, Ethernet, Fibre  
Channel, Serial ATA, and HDTV  
Cost-Effective High-Frequency Crystal  
Oscillator Replacement  
2x Output Available:  
–
Pin-Selectable Between LVPECL, LVDS, or  
2-LVCMOS; Operates at 3.3 V  
•
•
•
LVCMOS Bypass Output Available  
Output Frequency Selectable by /1, /2, /3, /4, /6,  
/8 from a Single Output Divider  
DESCRIPTION  
•
Supports Common LVPECL/LVDS Output  
Frequencies:  
The CDCM61002 is a highly versatile, low-jitter  
frequency synthesizer that can generate two low-jitter  
clock outputs, selectable between low-voltage  
positive emitter coupled logic (LVPECL), low-voltage  
differential signaling (LVDS), or low-voltage  
–
62.5 MHz, 74.25 MHz, 75 MHz, 77.76 MHz,  
100 MHz, 106.25 MHz, 125 MHz, 150 MHz,  
155.52 MHz, 156.25 MHz, 159.375 MHz,  
187.5 MHz, 200 MHz, 212.5 MHz, 250 MHz,  
311.04 MHz, 312.5 MHz, 622.08 MHz,  
625 MHz  
complementary  
metal  
oxide  
semiconductor  
(LVCMOS) outputs, from a low-frequency crystal or  
LVCMOS input for a variety of wireline and data  
communication applications. The CDCM61002  
features an onboard PLL that can be easily  
configured solely through control pins. The overall  
output random jitter performance is less than 1ps,  
RMS (from 10 kHz to 20 MHz), making this device a  
perfect choice for use in demanding applications such  
as SONET, Ethernet, Fibre Channel, and SAN. The  
CDCM61002 is available in a small, 32-pin, 5-mm ×  
5-mm QFN package.  
•
•
Supports Common LVCMOS Output  
Frequencies:  
–
62.5 MHz, 74.25 MHz, 75 MHz, 77.76 MHz,  
100 MHz, 106.25 MHz, 125 MHz, 150 MHz,  
155.52 MHz, 156.25 MHz, 159.375 MHz,  
187.5 MHz, 200 MHz, 212.5 MHz, 250 MHz  
Output Frequency Range: 43.75 MHz to  
683.264 MHz (See Table 3)  
•
•
Internal PLL Loop Bandwidth: 400 kHz  
High-Performance PLL Core:  
–
Phase Noise typically at –146 dBc/Hz at  
5-MHz Offset for 625-MHz LVPECL Output  
–
Random Jitter typically at 0.509 ps, RMS  
(10 kHz to 20 MHz) for 625-MHz LVPECL  
Output  
•
•
•
Output Duty Cycle Corrected to 50% (± 5%)  
Low Output Skew of 20 ps on LVPECL Outputs  
Divider Programming Using Control Pins:  
–
Two Pins for Prescaler/Feedback Divider  
Three Pins for Output Divider  
–
–
Two Pins for Output Select  
1
space  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
space Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
All trademarks are the property of their respective owners.  
2
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2009, Texas Instruments Incorporated  
1234567...34

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CDCM61002RHBT 替代型号

型号 品牌 替代类型 描述 数据表
CDCM61002RHBR TI

完全替代

 Two Output, Integrated VCO, Low-Jitter Clock Generator
CDCM61004RHBT TI

类似代替

 Four Output, Integrated VCO, Low-Jitter Clock Generator
CDCM61001RHBT TI

类似代替

 One Output, Integrated VCO, Low-Jitter Clock Generator

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