CDCLVD1204

更新时间： 2024-11-30 11:07:51

品牌	Logo	应用领域
德州仪器 - TI		时钟驱动时钟驱动器
页数	文件大小	规格书
20页	756K
描述
低抖动 2 路输入可选 1:4 通用至 LVDS 缓冲器

阅读下载

中文翻译

获取价格

数据手册
替代型号

如果您发现信息不准确，欢迎纠错

CDCLVD1204 数据手册

CDCLVD1204

www.ti.com

SCAS898A –MAY 2010–REVISED JUNE 2010

2:4 Low Additive Jitter LVDS Buffer

Check for Samples: CDCLVD1204

FEATURES

DESCRIPTION

•

2:4 Differential Buffer

The CDCLVD1204 clock buffer distributes one of two

selectable clock inputs, (IN0, IN1), to 4 pairs of

differential LVDS clock outputs (OUT0, OUT3) with

minimum skew for clock distribution. The

CDCLVD1204 can accept two clock sources into an

input multiplexer. The inputs can either be LVDS,

LVPECL, or LVCMOS.

•

Low Additive Jitter: <300 fs RMS in 10-kHz to

20-MHz

•

Low Output Skew of 20 ps (Max)

Universal Inputs Accept LVDS, LVPECL, and

LVCMOS

•

Selectable Clock Inputs through Control Pin

The CDCLVD1204 is specifically designed for driving

50 Ω transmission lines. In case of driving the inputs

in single ended mode, the appropriate bias voltage

(V_{AC_REF}) should be applied to the unused negative

input pin.

4 LVDS Outputs, ANSI EAI/TIA-644A Standard

Compatible

•

Clock Frequency up to 800 MHz

2.375 V–2.625 V Device Power Supply

The IN_SEL pin selects the input which is routed to

the outputs. If this pin is left open it disables the

outputs (static). The part supports a fail safe function.

The device incorporates an input hysteresis which

prevents random oscillation of the outputs in the

absence of an input signal.

LVDS Reference Voltage, V_{AC_REF}, Available for

Capacitive Coupled Inputs

•

Industrial Temperature Range: –40°C to 85°C

Packaged in 3 mm × 3 mm 16-Pin QFN (RGT)

ESD Protection Exceeds 3 kV HBM, 1 kV CDM

The device operates in 2.5V supply environment and

is characterized from –40°C to 85°C (ambient

temperature). The CDCLVD1204 is packaged in

small 16-pin, 3-mm × 3-mm QFN package.

APPLICATIONS

•

Telecommunications/Networking

Medical Imaging

Test and Measurement Equipment

Wireless Communications

General Purpose Clocking

ASIC

PHY1

PHY2

156.25 MHz

Oscillator

(156.25

MHz)

CDCLVD1204

LVDS Buffer

IN_SEL

FPGA

Figure 1. Application Example

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7...20

中文翻译

下载PDF

CDCLVD1204 替代型号

型号	品牌	替代类型	描述	数据表
CDCLVD2108	TI	功能相似	Dual 1:8 Low Additive Jitter LVDS Buffer
CDCLVD110A	TI	功能相似	PROGRAMMABLE LOW-VOLTAGE 1:10 LVDS CLOCK DRIVER

与CDCLVD1204相关器件

型号	品牌	获取价格	描述	数据表
CDCLVD1204RGTR	TI	获取价格	2:4 Low Additive Jitter LVDS Buffer
CDCLVD1204RGTT	TI	获取价格	2:4 Low Additive Jitter LVDS Buffer
CDCLVD1208	TI	获取价格	2:8 Low Additive Jitter LVDS Buffer
CDCLVD1208RHDR	TI	获取价格	2:8 Low Additive Jitter LVDS Buffer
CDCLVD1208RHDT	TI	获取价格	2:8 Low Additive Jitter LVDS Buffer
CDCLVD1212	TI	获取价格	2:12 Low Additive Jitter LVDS Buffer
CDCLVD1212RHAR	TI	获取价格	2:12 Low Additive Jitter LVDS Buffer
CDCLVD1212RHAT	TI	获取价格	2:12 Low Additive Jitter LVDS Buffer
CDCLVD1213	TI	获取价格	1:4 Low Additive Jitter LVDS Buffer With Divider
CDCLVD1213RGTR	TI	获取价格	1:4 Low Additive Jitter LVDS Buffer With Divider

与CDCLVD1204相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

49
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

38
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

67
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

62

产品中心

服务支持

精选活动

关于我们

帮助中心

CDCLVD1204

CDCLVD1204 数据手册

CDCLVD1204 替代型号

与CDCLVD1204相关器件

与CDCLVD1204相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CDCLVD1204

CDCLVD1204 数据手册

CDCLVD1204 替代型号

与CDCLVD1204相关器件

与CDCLVD1204相关文章

您还可以找

您在本页遇到什么问题？