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CDCLVD2102

更新时间： 2024-02-22 15:02:08
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
20页 753K
描述
Dual 1:2 Low Additive Jitter LVDS Buffer

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CDCLVD2102 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFN
包装说明：QFN-16针数：16
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：6 weeks
风险等级：1.26Is Samacsys：N
系列：CDC输入调节：DIFFERENTIAL
JESD-30 代码：S-PQCC-N16JESD-609代码：e4
长度：3 mm逻辑集成电路类型：LOW SKEW CLOCK DRIVER
湿度敏感等级：2功能数量：2
反相输出次数：端子数量：16
实输出次数：1最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：HVQCCN封装等效代码：LCC16,.12SQ,20
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
包装方法：TR峰值回流温度（摄氏度）：260
电源：2.5 VProp。Delay @ Nom-Sup：2.5 ns
传播延迟（tpd）：2.5 ns认证状态：Not Qualified
Same Edge Skew-Max（tskwd）：0.015 ns座面最大高度：1 mm
子类别：Clock Driver最大供电电压 (Vsup)：2.625 V
最小供电电压 (Vsup)：2.375 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：3 mm
最小 fmax：800 MHzBase Number Matches：1

CDCLVD2102 数据手册

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CDCLVD2102  
www.ti.com  
SCAS904A –MAY 2010–REVISED JUNE 2010  
Dual 1:2 Low Additive Jitter LVDS Buffer  
Check for Samples: CDCLVD2102  
1
FEATURES  
DESCRIPTION  
•
Dual 1:2 Differential Buffer  
•
Low Additive Jitter <300 fs RMS in 10-kHz to  
20-MHz  
The CDCLVD2102 clock buffer distributes two clock  
inputs (IN0, IN1) to a total of 4 pairs of differential  
LVDS clock outputs (OUT0, OUT3). Each buffer block  
consists of one input and 2 LVDS outputs. The inputs  
can either be LVDS, LVPECL, or LVCMOS.  
•
•
Low Within Bank Output Skew of 15 ps (Max)  
Universal Inputs Accept LVDS, LVPECL,  
LVCMOS  
The CDCLVD2102 is specifically designed for driving  
50-Ω transmission lines. If driving the inputs in single  
•
•
One Input Dedicated for Two Outputs  
Total of 4 LVDS Outputs, ANSI EIA/TIA-644A  
Standard Compatible  
ended mode, the appropriate bias voltage (VAC_REF  
)
should be applied to the unused negative input pin.  
•
•
•
Clock Frequency up to 800 MHz  
2.375–2.625V Device Power Supply  
Using the control pin (EN), outputs can be either  
disabled or enabled. If the EN pin is left open two  
buffers with all outputs are enabled, if switched to a  
logical "0" both buffers with all outputs are disabled  
(static logical "0"), if switched to a logical "1", one  
buffer with two outputs is disabled and another buffer  
with two outputs is enabled. The part supports a fail  
safe function. It incorporates an input hysteresis,  
which prevents random oscillation of the outputs in  
absence of an input signal.  
LVDS Reference Voltage, VAC_REF, Available for  
Capacitive Coupled Inputs  
•
•
•
Industrial Temperature Range –40°C to 85°C  
Packaged in 3mm × 3mm 16-Pin QFN (RGT)  
ESD Protection Exceeds 3 kV HBM, 1 kV CDM  
APPLICATIONS  
The device operates in 2.5V supply environment and  
is characterized from –40°C to 85°C (ambient  
temperature). The CDCLVD2102 is packaged in  
small 16-pin, 3-mm × 3-mm QFN package.  
•
•
•
•
•
Telecommunications/Networking  
Medical Imaging  
Test and Measurement Equipment  
Wireless Communications  
General Purpose Clocking  
200 MHz  
DAC2  
Clock  
EN  
Generation  
CDCLVD2102  
100 MHz  
ADC2  
Figure 1. Application Example  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2010, Texas Instruments Incorporated  
 
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