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CDCLVP111VF PDF预览

CDCLVP111VF

更新时间： 2024-09-26 06:47:07
品牌 Logo 应用领域
德州仪器 - TI 时钟驱动器逻辑集成电路输入元件PC
页数 文件大小 规格书
15页 618K
描述
LOW-VOLTAGE 1:10 LVPECL WITH SELECTABLE INPUT CLOCK DRIVER

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中文翻译

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CDCLVP111VF 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：QFP
包装说明：LQFP-32针数：32
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：1.67Samacsys Confidence：
Samacsys Status：ReleasedSamacsys PartID：605457
Samacsys Pin Count：32Samacsys Part Category：Integrated Circuit
Samacsys Package Category：OtherSamacsys Footprint Name：QFP80P900X900X145-32N
Samacsys Released Date：2017-01-12 12:59:53Is Samacsys：N
其他特性：LVECL MODE: VCC = 0V WITH VEE = -2.375V TO -3.8V; ALSO OPERATES AT 3.3 V SUPPLY系列：111
输入调节：DIFFERENTIAL MUXJESD-30 代码：S-PQFP-G32
JESD-609代码：e4长度：7 mm
逻辑集成电路类型：LOW SKEW CLOCK DRIVER最大I（ol）：0.005 A
湿度敏感等级：1功能数量：1
反相输出次数：端子数量：32
实输出次数：10最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装等效代码：QFP32,.35SQ,32
封装形状：SQUARE封装形式：FLATPACK, LOW PROFILE
包装方法：TRAY峰值回流温度（摄氏度）：260
电源：+-2.5/+-3.3 V最大电源电流（ICC）：85 mA
Prop。Delay @ Nom-Sup：0.35 ns传播延迟（tpd）：0.35 ns
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.03 ns
座面最大高度：1.6 mm子类别：Clock Drivers
最大供电电压 (Vsup)：3.8 V最小供电电压 (Vsup)：2.375 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.8 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7 mm最小 fmax：3500 MHz
Base Number Matches：1

CDCLVP111VF 数据手册

 浏览型号CDCLVP111VF的Datasheet PDF文件第2页浏览型号CDCLVP111VF的Datasheet PDF文件第3页浏览型号CDCLVP111VF的Datasheet PDF文件第4页浏览型号CDCLVP111VF的Datasheet PDF文件第5页浏览型号CDCLVP111VF的Datasheet PDF文件第6页浏览型号CDCLVP111VF的Datasheet PDF文件第7页 
CDCLVP111  
www.ti.com  
SCAS859D –JANUARY 2009–REVISED MARCH 2010  
LOW-VOLTAGE 1:10 LVPECL  
WITH SELECTABLE INPUT CLOCK DRIVER  
Check for Samples: CDCLVP111  
1
FEATURES  
APPLICATIONS  
•
•
Designed for Driving 50 Ω Transmission Lines  
High Performance Clock Distribution  
2
•
Distributes One Differential Clock Input Pair  
LVPECL to 10 Differential LVPECL  
•
•
Fully Compatible With LVECL/LVPECL  
LQFP AND QFN PACKAGE  
(TOP VIEW)  
Supports a Wide Supply Voltage Range From  
2.375 V to 3.8 V  
•
•
Selectable Clock Input Through CLK_SEL  
Low-Output Skew (Typ 15 ps) for  
Clock-Distribution Applications  
–
–
–
–
Additive Jitter Less Than 1 ps  
Propagation Delay Less Than 350 ps  
Open Input Default State  
PowerPAD  
(0)  
LVDS, CML, SSTL input compatible  
•
VBB Reference Voltage Output for  
Single-Ended Clocking  
•
•
•
Available in a 32-Pin LQFP and QFN Package  
Frequency Range From DC to 3.5 GHz  
Pin-to-Pin Compatible With MC100 Series  
EP111, ES6111, LVEP111, PTN1111  
DESCRIPTION  
The CDCLVP111 clock driver distributes one differential clock pair of LVPECL input, (CLK0, CLK1) to ten pairs of  
differential LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution. The CDCLVP111 can  
accept two clock sources into an input multiplexer. The CDCLVP111 is specifically designed for driving 50-Ω  
transmission lines. When an output pin is not used, leaving it open is recommended to reduce power  
consumption. If only one of the output pins from a differential pair is used, the other output pin must be identically  
terminated to 50 Ω.  
The VBB reference voltage output is used if single-ended input operation is required. In this case, the VBB pin  
should be connected to CLK0 and bypassed to GND via a 10-nF capacitor.  
However, for high-speed performance up to 3.5 GHz, the differential mode is strongly recommended.  
The CDCLVP111 is characterized for operation from –40°C to 85°C.  
Table 1. FUNCTION TABLE  
CLK_SEL  
ACTIVE CLOCK INPUT  
CLK0, CLK0  
0
1
CLK1, CLK1  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
PowerPAD is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2009–2010, Texas Instruments Incorporated  
 
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中文翻译

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CDCLVP111VF 替代型号

型号 品牌 替代类型 描述 数据表
CDCLVP111VFR TI

完全替代

 LOW-VOLTAGE 1:10 LVPECL WITH SELECTABLE INPUT CLOCK DRIVER
CDCLVP111RHBT TI

完全替代

 LOW-VOLTAGE 1:10 LVPECL WITH SELECTABLE INPUT CLOCK DRIVER
CDCLVP111RHBR TI

完全替代

 LOW-VOLTAGE 1:10 LVPECL WITH SELECTABLE INPUT CLOCK DRIVER

与CDCLVP111VF相关器件

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CDCLVP111VFR TI

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 		LOW-VOLTAGE 1:10 LVPECL WITH SELECTABLE INPUT CLOCK DRIVER
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CDCLVP1204_15 TI

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 		Four LVPECL Output, High-Performance Clock Buffer
CDCLVP1204RGTR TI

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 		Four LVPECL Output, High-Performance Clock Buffer
CDCLVP1204RGTT TI

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 		Four LVPECL Output, High-Performance Clock Buffer
CDCLVP1208 TI

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 		Eight LVPECL Output, High-Performance Clock 2:8 Buffer
CDCLVP1208RHDR TI

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 		Eight LVPECL Output, High-Performance Clock 2:8 Buffer
CDCLVP1208RHDT TI

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 		Eight LVPECL Output, High-Performance Clock 2:8 Buffer
CDCLVP1212 TI

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 		12 LVPECL Output, High-Performance Clock Buffer
CDCLVP1212RHAR TI

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 		12 LVPECL Output, High-Performance Clock Buffer

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