5秒后页面跳转
CDCLVP2102 PDF预览

CDCLVP2102

更新时间: 2024-11-24 12:55:11
品牌 Logo 应用领域
德州仪器 - TI 时钟
页数 文件大小 规格书
22页 756K
描述
Four LVPECL Output, High-Performance Clock Buffer

CDCLVP2102 数据手册

 浏览型号CDCLVP2102的Datasheet PDF文件第2页浏览型号CDCLVP2102的Datasheet PDF文件第3页浏览型号CDCLVP2102的Datasheet PDF文件第4页浏览型号CDCLVP2102的Datasheet PDF文件第5页浏览型号CDCLVP2102的Datasheet PDF文件第6页浏览型号CDCLVP2102的Datasheet PDF文件第7页 
CDCLVP2102  
www.ti.com  
SCAS881B AUGUST 2009REVISED AUGUST 2011  
Four LVPECL Output,  
High-Performance Clock Buffer  
Check for Samples: CDCLVP2102  
1
FEATURES  
DESCRIPTION  
The CDCLVP2102 is a highly versatile, low additive  
2
Dual 1:2 Differential Buffer  
Two Clock Inputs  
jitter buffer that can generate four copies of LVPECL  
clock outputs from two LVPECL, LVDS, or LVCMOS  
inputs for a variety of communication applications. It  
has a maximum clock frequency up to 2 GHz. Each  
buffer block consists of one input that feeds two  
LVPECL outputs. The overall additive jitter  
performance is less than 0.1 ps, RMS from 10 kHz to  
20 MHz, and overall output skew is as low as 10 ps,  
making the device a perfect choice for use in  
demanding applications.  
Universal Inputs Can Accept LVPECL, LVDS,  
LVCMOS/LVTTL  
Four LVPECL Outputs  
Maximum Clock Frequency: 2 GHz  
Maximum Core Current Consumption: 48 mA  
Very Low Additive Jitter: <100 fs,rms in 10-kHz  
to 20-MHz Offset Range  
The CDCLVP2102 clock buffer distributes two clock  
inputs (IN0, IN1) to four pairs of differential LVPECL  
clock outputs (OUT0, OUT3) with minimum skew for  
clock distribution. Each buffer block consists of one  
input that feeds two LVPECL clock outputs. The  
inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.  
2.375-V to 3.6-V Device Power Supply  
Maximum Propagation Delay: 450 ps  
Maximum Within Bank Output Skew: 10 ps  
LVPECL Reference Voltage, VAC_REF, Available  
for Capacitive-Coupled Inputs  
Industrial Temperature Range: 40°C to +85°C  
The CDCLVP2102 is specifically designed for driving  
50-transmission lines. When driving the inputs in  
single-ended mode, the LVPECL bias voltage  
(VAC_REF) should be applied to the unused negative  
input pin. However, for high-speed performance up to  
2 GHz, differential mode is strongly recommended.  
Available in 3-mm × 3-mm QFN-16 (RGT)  
Package  
ESD Protection Exceeds 2 kV (HBM)  
APPLICATIONS  
The CDCLVP2102 is characterized for operation  
from 40°C to +85°C and is available in a QFN-16,  
3-mm × 3-mm package.  
Wireless Communications  
Telecommunications/Networking  
Medical Imaging  
Test and Measurement Equipment  
VCC  
OUTP[1,0]  
INP0  
INN0  
2
LVPECL  
OUTN[1,0]  
2
OUTP[3,2]  
INP1  
INN1  
2
LVPECL  
OUTN[3,2]  
2
Reference  
Generator  
VAC_REF  
GND  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
All trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 20092011, Texas Instruments Incorporated  

与CDCLVP2102相关器件

型号 品牌 获取价格 描述 数据表
CDCLVP2102_16 TI

获取价格

Four-LVPECL Output, High-Performance Clock Buffer
CDCLVP2102RGTR TI

获取价格

Four LVPECL Output, High-Performance Clock Buffer
CDCLVP2102RGTT TI

获取价格

Four LVPECL Output, High-Performance Clock Buffer
CDCLVP2104 TI

获取价格

Eight LVPECL Output, High-Performance Clock Buffer
CDCLVP2104_16 TI

获取价格

Eight-LVPECL Output, High-Performance Clock Buffer
CDCLVP2104RHDR TI

获取价格

Eight LVPECL Output, High-Performance Clock Buffer
CDCLVP2104RHDT TI

获取价格

Eight LVPECL Output, High-Performance Clock Buffer
CDCLVP2106 TI

获取价格

12 LVPECL Output, High-Performance Clock Buffer
CDCLVP2106_16 TI

获取价格

12-LVPECL Output, High-Performance Clock Buffer
CDCLVP2106RHAR TI

获取价格

12 LVPECL Output, High-Performance Clock Buffer