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CDCM1804 PDF预览

CDCM1804

更新时间: 2024-11-05 22:29:23
品牌 Logo 应用领域
德州仪器 - TI 输出元件时钟
页数 文件大小 规格书
24页 580K
描述
1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER

CDCM1804 数据手册

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CDCM1804  
www.ti.com  
SCAS697EJULY 2003REVISED MAY 2005  
1:3 LVPECL CLOCK BUFFER + ADDITIONAL  
LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER  
The CDCM1804 is characterized for operation from  
–40°C to 85°C.  
FEATURES  
Distributes One Differential Clock Input to  
Three LVPECL Differential Clock Outputs and  
One LVCMOS Single-Ended Output  
For use in single-ended driver applications, the  
CDCM1804 also provides a VBB output terminal that  
can be directly connected to the unused input as a  
common-mode voltage reference.  
Programmable Output Divider for Two  
LVPECL Outputs and LVCMOS Output  
Low-Output Skew 15 ps (Typical) for  
Clock-Distribution Applications for LVPECL  
Outputs; 1.6-ns Output Skew Between  
LVCMOS and LVPECL Transitions Minimizing  
Noise  
RGE PACKAGE  
(TOP VIEW)  
VCC Range 3 V–3.6 V  
24 23 22 21 20 19  
EN  
PECL  
IN  
1
2
3
4
5
6
18  
17  
16  
15  
14  
13  
S0  
Signaling Rate Up to 800-MHz LVPECL and  
200-MHz LVCMOS  
V
V
V
DD  
1
DD  
Differential Input Stage for Wide  
Common-Mode Range  
Y1  
Y1  
(1)  
SS  
V
IN  
Provides VBB Bias Voltage Output for  
Single-Ended Input Signals  
PECL  
VBB  
V
DD  
V
DD  
1
3
DD  
Receiver Input Threshold ±75 mV  
7
8
9
10 11 12  
24-Terminal QFN Package (4 mm × 4 mm)  
Accepts Any Differential Signaling:  
LVDS, HSTL, CML, VML, SSTL-2, and  
Single-Ended: LVTTL/LVCMOS  
(1)  
Thermal pad must be connected to V  
.
SS  
P0024-01  
DESCRIPTION  
RTH PACKAGE  
(TOP VIEW)  
The CDCM1804 clock driver distributes one pair of  
differential clock inputs to three pairs of LVPECL  
differential clock outputs Y[2:0] and Y[2:0], with mini-  
mum skew for clock distribution. The CDCM1804 is  
specifically designed for driving 50-transmission  
lines. Additionally, the CDCM1804 offers  
a
1
2
3
4
5
6
18  
17  
16  
15  
14  
13  
EN  
PECL  
IN  
S0  
V
single-ended LVCMOS output Y3. This output is  
delayed by 1.6 ns over the three LVPECL output  
stages to minimize noise impact during signal tran-  
sitions.  
V
1
DD  
DD  
Y1  
Y1  
(1)  
SS  
V
IN  
The CDCM1804 has three control terminals, S0, S1,  
and S2, to select different output mode settings. The  
S[2:0] terminals are 3-level inputs and therefore allow  
up to 33 = 27 combinations. Additionally, an enable  
terminal (EN) is provided to disable or enable all  
outputs simultaneously. The EN terminal is a 3-level  
input as well and extends the number of settings to  
2 × 27 = 54. See Table 1 for details.  
V
DD  
PECL  
VBB  
V
DD  
V
DD  
1
3
(1)  
Thermal pad must be connected to V  
.
SS  
P0025-01  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2003–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  

CDCM1804 替代型号

型号 品牌 替代类型 描述 数据表
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