CDCM1804RGET

更新时间： 2024-11-08 22:16:39

品牌	Logo	应用领域
德州仪器 - TI		时钟驱动器逻辑集成电路输出元件
页数	文件大小	规格书
24页	580K
描述
1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER

阅读下载

中文翻译

获取价格

技术参数
数据手册
替代型号

如果您发现信息不准确，欢迎纠错

CDCM1804RGET 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	QFN
包装说明：	HVQCCN, LCC24,.16SQ,20	针数：	24
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	Factory Lead Time：	1 week
风险等级：	1.12	其他特性：	3 LVPECL DIFFERENTIAL CLOCK OUTPUTS AND SINGLE ENDED LVCMOS OUTPUT
系列：	1803	输入调节：	DIFFERENTIAL
JESD-30 代码：	S-PQCC-N24	JESD-609代码：	e4
长度：	4 mm	逻辑集成电路类型：	LOW SKEW CLOCK DRIVER
最大I（ol）：	0.012 A	湿度敏感等级：	2
功能数量：	1	反相输出次数：
端子数量：	24	实输出次数：	4
最高工作温度：	85 °C	最低工作温度：	-40 °C
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	HVQCCN	封装等效代码：	LCC24,.16SQ,20
封装形状：	SQUARE	封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
包装方法：	TR	峰值回流温度（摄氏度）：	260
电源：	3.3 V	Prop。Delay @ Nom-Sup：	0.6 ns
传播延迟（tpd）：	2.6 ns	认证状态：	Not Qualified
Same Edge Skew-Max（tskwd）：	0.03 ns	座面最大高度：	1 mm
子类别：	Clock Drivers	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	温度等级：	INDUSTRIAL
端子面层：	Nickel/Palladium/Gold (Ni/Pd/Au)	端子形式：	NO LEAD
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	4 mm
最小 fmax：	800 MHz	Base Number Matches：	1

CDCM1804RGET 数据手册

CDCM1804

www.ti.com

SCAS697E–JULY 2003–REVISED MAY 2005

1:3 LVPECL CLOCK BUFFER + ADDITIONAL

LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER

The CDCM1804 is characterized for operation from

–40°C to 85°C.

FEATURES

•

Distributes One Differential Clock Input to

Three LVPECL Differential Clock Outputs and

One LVCMOS Single-Ended Output

For use in single-ended driver applications, the

CDCM1804 also provides a VBB output terminal that

can be directly connected to the unused input as a

common-mode voltage reference.

•

Programmable Output Divider for Two

LVPECL Outputs and LVCMOS Output

Low-Output Skew 15 ps (Typical) for

Clock-Distribution Applications for LVPECL

Outputs; 1.6-ns Output Skew Between

LVCMOS and LVPECL Transitions Minimizing

Noise

RGE PACKAGE

(TOP VIEW)

•

V_CCRange 3 V–3.6 V

24 23 22 21 20 19

PECL

Signaling Rate Up to 800-MHz LVPECL and

200-MHz LVCMOS

•

Differential Input Stage for Wide

Common-Mode Range

(1)

Provides VBB Bias Voltage Output for

Single-Ended Input Signals

PECL

VBB

•

Receiver Input Threshold ±75 mV

10 11 12

24-Terminal QFN Package (4 mm × 4 mm)

Accepts Any Differential Signaling:

LVDS, HSTL, CML, VML, SSTL-2, and

Single-Ended: LVTTL/LVCMOS

(1)

Thermal pad must be connected to V

P0024-01

DESCRIPTION

RTH PACKAGE

(TOP VIEW)

The CDCM1804 clock driver distributes one pair of

differential clock inputs to three pairs of LVPECL

differential clock outputs Y[2:0] and Y[2:0], with mini-

mum skew for clock distribution. The CDCM1804 is

specifically designed for driving 50-Ω transmission

lines. Additionally, the CDCM1804 offers

PECL

single-ended LVCMOS output Y3. This output is

delayed by 1.6 ns over the three LVPECL output

stages to minimize noise impact during signal tran-

sitions.

(1)

The CDCM1804 has three control terminals, S0, S1,

and S2, to select different output mode settings. The

S[2:0] terminals are 3-level inputs and therefore allow

up to 3³= 27 combinations. Additionally, an enable

terminal (EN) is provided to disable or enable all

outputs simultaneously. The EN terminal is a 3-level

input as well and extends the number of settings to

2 × 27 = 54. See Table 1 for details.

PECL

VBB

(1)

Thermal pad must be connected to V

P0025-01

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7...24

中文翻译

下载PDF

CDCM1804RGET 替代型号

型号	品牌	替代类型	描述	数据表
CDCM1804RGETG4	TI	完全替代	1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER
CDCM1804RGERG4	TI	完全替代	1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER
CDCM1804RGER	TI	完全替代	1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER

与CDCM1804RGET相关器件

型号	品牌	获取价格	描述	数据表
CDCM1804RGETG4	TI	获取价格	1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER
CDCM1804RTHR	TI	获取价格	1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER
CDCM1804RTHT	TI	获取价格	1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER
CDCM61001	TI	获取价格	One Output, Integrated VCO, Low-Jitter Clock Generator
CDCM61001_10	TI	获取价格	One Output, Integrated VCO, Low-Jitter Clock Generator
CDCM61001_12	TI	获取价格	One Output, Integrated VCO, Low-Jitter Clock Generator
CDCM61001RHBR	TI	获取价格	One Output, Integrated VCO, Low-Jitter Clock Generator
CDCM61001RHBR/2801	TI	获取价格	1:1 超低抖动晶振时钟发生器 \| RHB \| 32 \| -40 to 85
CDCM61001RHBT	TI	获取价格	One Output, Integrated VCO, Low-Jitter Clock Generator
CDCM61002	TI	获取价格	Two Output, Integrated VCO, Low-Jitter Clock Generator

与CDCM1804RGET相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

22
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

21
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

47
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

39

产品中心

服务支持

精选活动

关于我们

帮助中心

CDCM1804RGET

CDCM1804RGET 技术参数

CDCM1804RGET 数据手册

CDCM1804RGET 替代型号

与CDCM1804RGET相关器件

与CDCM1804RGET相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CDCM1804RGET

CDCM1804RGET 技术参数

CDCM1804RGET 数据手册

CDCM1804RGET 替代型号

与CDCM1804RGET相关器件

与CDCM1804RGET相关文章

您还可以找

您在本页遇到什么问题？