Datasheet > CDCM1802

CDCM1802

更新时间： 2024-11-08 21:55:39

品牌	Logo	应用领域
德州仪器 - TI		输出元件时钟
页数	文件大小	规格书
22页	693K
描述
CLOCK BUFFER WITH PROGRAMMABLE DIVIDER, LVPECL I/O + ADDITIONAL LVCMOS OUTPUT

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CDCM1802 数据手册

CDCM1802

CLOCK BUFFER WITH PROGRAMMABLE DIVIDER,

LVPECL I/O + ADDITIONAL LVCMOS OUTPUT

SCAS759 − APRIL 2004

QFN PACKAGE

(TOP VIEW)

Distributes One Differential Clock Input to

One LVPECL Differential Clock Output and

One LVCMOS Single-Ended Output

Programmable Output Divider for Both

LVPECL and LVCMOS Outputs

1.6-ns Output Skew Between LVCMOS and

LVPECL Transitions Minimizing Noise

PECL

3.3-V Power Supply (2.5-V Functional)

Signaling Rate Up to 800-MHz LVPECL and

200-MHz LVCMOS

10 Y0

VBB

Differential Input Stage for Wide

Common-Mode Range Also Provides VBB

Bias Voltage Output for Single-Ended Input

Signals

Receiver Input Threshold 75 mV

16-Pin QFN Package (3 mm x 3 mm)

description

The CDCM1802 clock driver distributes one pair of differential clock input to one LVPECL differential clock

output pair Y0 and Y0 and one single-ended LVCMOS output Y1. It is specifically designed for driving 50-Ω

transmission lines. The LVCMOS output is delayed by 1.6 ns over the PECL output stage to minimize noise

impact during signal transitions.

The CDCM1802 has two control pins, S0 and S1, to select different output mode settings. The S[1:0] pins are

3-level inputs. Additionally, an enable pin EN is provided to disable or enable all outputs simultaneously. The

CDCM1802 is characterized for operation from −40°C to 85°C.

For single-ended driver applications, the CDCM1802 provides a VBB output pin that can be directly connected

to the unused input as a common-mode voltage reference.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...22

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CDCM1802 替代型号

型号	品牌	替代类型	描述	数据表
LMK01000	TI	功能相似	具有 3 个 LVDS 和 5 个 LVPECL 输出的 1.6GHz 高性能时钟缓冲器、
CDCP1803	TI	功能相似	1:3 LVPECL CLOCK BUFFER WITH PROGRAMMABLE DIVIDER
CDCM1804	TI	功能相似	1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER

与CDCM1802相关器件

型号	品牌	获取价格	描述	数据表
CDCM1802RGTR	TI	获取价格	CLOCK BUFFER WITH PROGRAMMABLE DIVIDER, LVPECL I/O + ADDITIONAL LVCMOS OUTPUT
CDCM1802RGTT	TI	获取价格	CLOCK BUFFER WITH PROGRAMMABLE DIVIDER, LVPECL I/O + ADDITIONAL LVCMOS OUTPUT
CDCM1804	TI	获取价格	1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER
CDCM1804_17	TI	获取价格	1:3 LVPECL CLOCK BUFFER ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER
CDCM1804RGER	TI	获取价格	1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER
CDCM1804RGERG4	TI	获取价格	1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER
CDCM1804RGET	TI	获取价格	1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER
CDCM1804RGETG4	TI	获取价格	1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER
CDCM1804RTHR	TI	获取价格	1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER
CDCM1804RTHT	TI	获取价格	1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER

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