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CDCLVP2106RHAT PDF预览

CDCLVP2106RHAT

更新时间： 2024-11-20 12:55:11
品牌 Logo 应用领域
德州仪器 - TI 时钟驱动器逻辑集成电路
页数 文件大小 规格书
23页 724K
描述
12 LVPECL Output, High-Performance Clock Buffer

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CDCLVP2106RHAT 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFN
包装说明：VQFN-40针数：40
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：1.27Is Samacsys：N
系列：CDC输入调节：DIFFERENTIAL
JESD-30 代码：S-PQCC-N40JESD-609代码：e4
长度：6 mm逻辑集成电路类型：LOW SKEW CLOCK DRIVER
湿度敏感等级：3功能数量：1
反相输出次数：端子数量：40
实输出次数：12最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：HVQCCN封装等效代码：LCC40,.24SQ,20
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
包装方法：TR峰值回流温度（摄氏度）：260
电源：2.5/3.3 V最大电源电流（ICC）：92 mA
Prop。Delay @ Nom-Sup：0.55 ns传播延迟（tpd）：0.55 ns
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.025 ns
座面最大高度：1 mm子类别：Clock Drivers
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.375 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：6 mm最小 fmax：2000 MHz
Base Number Matches：1

CDCLVP2106RHAT 数据手册

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CDCLVP2106  
www.ti.com  
SCAS887A –SEPTEMBER 2009–REVISED AUGUST 2011  
12 LVPECL Output, High-Performance Clock Buffer  
Check for Samples: CDCLVP2106  
1
FEATURES  
DESCRIPTION  
The CDCLVP2106 is a highly versatile, low additive  
jitter buffer that can generate 12 copies of LVPECL  
clock outputs from two LVPECL, LVDS, or LVCMOS  
inputs for a variety of communication applications. It  
has a maximum clock frequency up to 2 GHz. Each  
buffer block consists of one input that feeds two  
LVPECL outputs. The overall additive jitter  
performance is less than 0.1 ps, RMS from 10 kHz to  
20 MHz, and overall output skew is as low as 20 ps,  
making the device a perfect choice for use in  
demanding applications.  
2
•
•
•
Dual 1:6 Differential Buffer  
Two Clock Inputs  
Universal Inputs Can Accept LVPECL, LVDS,  
LVCMOS/LVTTL  
•
•
•
•
12 LVPECL Outputs  
Maximum Clock Frequency: 2 GHz  
Maximum Core Current Consumption: 92 mA  
Very Low Additive Jitter: <100 fs,rms in 10-kHz  
to 20-MHz Offset Range  
The CDCLVP2106 clock buffer distributes two clock  
inputs (IN0, IN1) to 12 pairs of differential LVPECL  
clock outputs (OUT0, OUT11) with minimum skew for  
clock distribution. Each buffer block consists of one  
input that feeds two LVPECL clock outputs. The  
inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.  
•
•
•
•
2.375-V to 3.6-V Device Power Supply  
Maximum Propagation Delay: 550 ps  
Maximum Within Bank Output Skew: 20 ps  
LVPECL Reference Voltage, VAC_REF, Available  
for Capacitive-Coupled Inputs  
•
•
Industrial Temperature Range: –40°C to +85°C  
The CDCLVP2106 is specifically designed for driving  
50-Ω transmission lines. When driving the inputs in  
single-ended mode, the LVPECL bias voltage  
(VAC_REF) should be applied to the unused negative  
input pin. However, for high-speed performance up to  
2 GHz, differential mode is strongly recommended.  
Available in 6-mm × 6-mm QFN-40 (RHA)  
Package  
•
ESD Protection Exceeds 2 kV (HBM)  
APPLICATIONS  
The CDCLVP2106 is characterized for operation  
from –40°C to +85°C and is available in a QFN-40,  
6-mm × 6-mm package.  
•
•
•
•
Wireless Communications  
Telecommunications/Networking  
Medical Imaging  
Test and Measurement Equipment  
VCC  
VCC  
VCC  
VCC  
VCC  
VCC  
OUTP[5...0]  
OUTN[5...0]  
INP0  
INN0  
6
6
LVPECL  
LVPECL  
OUTP[11...6]  
OUTN[11...6]  
INP1  
INN1  
6
6
Reference  
Generator  
VAC_REF[1, 0]  
2
GND  
GND  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
All trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2009–2011, Texas Instruments Incorporated  
1234567...23

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CDCLVP2106RHAT 替代型号

型号 品牌 替代类型 描述 数据表
CDCLVP2106RHAR TI

完全替代

 12 LVPECL Output, High-Performance Clock Buffer

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