CDCLVD2104RHDT

更新时间： 2024-01-30 12:08:42

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德州仪器 - TI		/
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21页	782K
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Dual 1:4 Low Additive Jitter LVDS Buffer

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CDCLVD2104RHDT 数据手册

CDCLVD2104

www.ti.com

SCAS903A –JUNE 2010–REVISED AUGUST 2010

Dual 1:4 Low Additive Jitter LVDS Buffer

Check for Samples: CDCLVD2104

FEATURES

DESCRIPTION

•

Dual 1:4 Differential Buffer

•

Low Additive Jitter <300 fs, RMS in

10 kHz to 20 MHz

The CDCLVD2104 clock buffer distributes two clock

inputs (IN0, IN1) to a total of 8 pairs of differential

LVDS clock outputs (OUT0, OUT7). Each buffer block

consists of one input and 4 LVDS outputs. The inputs

can either be LVDS, LVPECL, or LVCMOS.

•

Low Within Bank Output Skew of 35ps (Max)

Universal Inputs Accept LVDS, LVPECL,

LVCMOS

The CDCLVD2104 is specifically designed for driving

50-Ω transmission lines. If the input is in single ended

mode, the appropriate bias voltage (V_{AC_REF}) should

be applied to the unused negative input pin.

•

One Input Dedicated for Four Output Buffers

8 LVDS Outputs, ANSI EIA/TIA-644A Standard

Compatible

•

Clock Frequency up to 800 MHz

2.375–2.625V Device Power Supply

Using the control pin (EN), outputs can be either

disabled or enabled. If the EN pin is left open two

buffers with all outputs are enabled, if switched to a

logical "0" both buffers with all outputs are disabled

(static logical “0”), if switched to a logical "1", one

buffer with four outputs is disabled and another buffer

with four outputs is enabled. The part supports a fail

safe function. It incorporates an input hysteresis,

which prevents random oscillation of the outputs in

absence of an input signal.

LVDS Reference Voltage, V_{AC_REF}, Available for

Capacitive Coupled Inputs

•

Industrial Temperature Range –40°C to 85°C

Packaged in 5mm × 5mm 28-Pin QFN (RHD)

ESD Protection Exceeds 3 kV HBM, 1 kV CDM

APPLICATIONS

The device operates in 2.5V supply environment and

is characterized from –40°C to 85°C (ambient

temperature). The CDCLVD2104 is packaged in

small 28-pin, 5-mm × 5-mm QFN package.

•

Telecommunications/Networking

Medical Imaging

Test and Measurement Equipment

Wireless Communications

General Purpose Clocking

200 MHz

PHY

DAC4

Clock

Generator

CDCLVD2104

100 MHz

PHY

ADC4

Figure 1. Application Example

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

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CDCLVD2104RHDT 替代型号

型号	品牌	替代类型	描述	数据表
CDCLVD2104RHDR	TI	类似代替	Dual 1:4 Low Additive Jitter LVDS Buffer

与CDCLVD2104RHDT相关器件

型号	品牌	获取价格	描述	数据表
CDCLVD2106	TI	获取价格	Dual 1:6 Low Additive Jitter LVDS Buffer
CDCLVD2106_14	TI	获取价格	Dual 1:6 Low Additive Jitter LVDS Buffer
CDCLVD2106RHAR	TI	获取价格	Dual 1:6 Low Additive Jitter LVDS Buffer
CDCLVD2106RHAT	TI	获取价格	Dual 1:6 Low Additive Jitter LVDS Buffer
CDCLVD2108	TI	获取价格	Dual 1:8 Low Additive Jitter LVDS Buffer
CDCLVD2108RGZR	TI	获取价格	Dual 1:8 Low Additive Jitter LVDS Buffer
CDCLVD2108RGZT	TI	获取价格	Dual 1:8 Low Additive Jitter LVDS Buffer
CDCLVP110	TI	获取价格	LOW-VOLTAGE 1:10 LVPECL/HSTL WITH SELECTABLE INPUT CLOCK DRIVER
CDCLVP1102	TI	获取价格	Two LVPECL Output, High-Performance Clock Buffer
CDCLVP1102RGTR	TI	获取价格	Two LVPECL Output, High-Performance Clock Buffer

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