5秒后页面跳转
捷配首页

Datasheet > CDC2509A_15
CDC2509A_15 PDF预览

CDC2509A_15

更新时间： 2024-11-19 02:58:43
品牌 Logo 应用领域
德州仪器 - TI 驱动
页数 文件大小 规格书
13页 431K
描述
3.3-V PHASE-LOCK LOOP CLOCK DRIVER

阅读下载

中文翻译

获取价格

CDC2509A_15 数据手册

 浏览型号CDC2509A_15的Datasheet PDF文件第2页浏览型号CDC2509A_15的Datasheet PDF文件第3页浏览型号CDC2509A_15的Datasheet PDF文件第4页浏览型号CDC2509A_15的Datasheet PDF文件第5页浏览型号CDC2509A_15的Datasheet PDF文件第6页浏览型号CDC2509A_15的Datasheet PDF文件第7页 
ꢀ ꢁꢀ ꢂꢃ ꢄꢅ ꢆ  
ꢇ ꢈꢇ ꢉꢊ ꢋꢌꢆ ꢍꢎꢉꢏ ꢐ ꢀꢑ ꢏ ꢐꢐ ꢋ ꢀꢏ ꢐ ꢀꢑ ꢁ ꢒꢓ ꢊ ꢎꢒ  
ꢔ
SCAS603C − APRIL 1998 − REVISED DECEMBER 2004  
PW PACKAGE  
(TOP VIEW)  
D
Use CDCVF2509A as a Replacement for  
this Device  
D
D
D
D
D
D
D
Spread Spectrum Clock Compatible  
100-MHz Maximum Frequency  
AGND  
CLK  
AV  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
V
2
CC  
CC  
Available in Plastic 24-Pin TSSOP  
1Y0  
1Y1  
1Y2  
GND  
GND  
1Y3  
V
3
CC  
2Y0  
2Y1  
GND  
GND  
2Y2  
2Y3  
4
Phase-Lock Loop Clock Distribution for  
Synchronous DRAM Applications  
5
6
Distributes One Clock Input to One Bank of  
Five and One Bank of Four Outputs  
7
8
Separate Output Enable for Each Output  
Bank  
1Y4  
9
V
10  
11  
12  
V
CC  
CC  
External Feedback (FBIN) Pin Is Used to  
Synchronize the Outputs to the Clock Input  
1G  
FBOUT  
2G  
FBIN  
D
D
D
On-Chip Series Damping Resistors  
No External RC Network Required  
Operates at 3.3-V V  
CC  
description  
The CDC2509A is a high-performance, lowkew, lo-jitter, phase-lock loop (PLL) clock driver. It uses a PLL  
to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.  
It is specifically designed for use with synchronous DRAMs. The CDC2509A operates at 3.3-V V  
integrated series-damping resistors hat mait ideal for driving point-to-point loads.  
and provides  
CC  
One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output  
signal duty cycles are adjustto 50 percent, independent of the duty cycle at CLK. Each bank of outputs can  
be enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs  
switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low  
state.  
Unlike many products containing PLLs, the CDC2509A does not require external RC networks. The loop filter  
for the PLL is luded on-chip, minimizing component count, board space, and cost.  
Because it is based on PLL circuitry, the CDC2509A requires a stabilization time to achieve phase lock of the  
feedback signal to the reference signal. This stabilization time is required, following power up and application  
of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback  
signals. The PLL can be bypassed for test purposes by strapping AV  
to ground.  
CC  
The CDC2509A is characterized for operation from 0°C to 70°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢋ
ꢋ
ꢒ
ꢐ
ꢧ
ꢁ
ꢢ
ꢕ
ꢀ
ꢠ
ꢖ
ꢡ
ꢓ
ꢛ
ꢐ
ꢙ
ꢗ
ꢚ
ꢁ
ꢆ
ꢖ
ꢆ
ꢘ
ꢙ
ꢣ
ꢚ
ꢛ
ꢡ
ꢜ
ꢝ
ꢞ
ꢞ
ꢟ
ꢟ
ꢘ
ꢘ
ꢛ
ꢛ
ꢙ
ꢙ
ꢘ
ꢠ
ꢠ
ꢤ
ꢡ
ꢢ
ꢜ
ꢜ
ꢣ
ꢣ
ꢙ
ꢟ
ꢞ
ꢝ
ꢠ
ꢠ
ꢛ
ꢚ
ꢤ
ꢖꢣ  
ꢢ
ꢥ
ꢠ
ꢦ
ꢘ
ꢡ
ꢞ
ꢠ
ꢟ
ꢘ
ꢟ
ꢛ
ꢜ
ꢙ
ꢢ
ꢧ
ꢞ
ꢙ
ꢟ
ꢟ
ꢣ
ꢠ
ꢈ
Copyright 2001 − 2004, Texas Instruments Incorporated  
ꢜ
ꢛ
ꢡ
ꢟ
ꢛ
ꢜ
ꢝ
ꢟ
ꢛ
ꢠ
ꢤ
ꢘ
ꢚ
ꢘ
ꢡ
ꢣ
ꢜ
ꢟ
ꢨ
ꢟ
ꢣ
ꢜ
ꢛ
ꢚ
ꢩ
ꢞ
ꢓ
ꢙ
ꢝ
ꢣ
ꢠ
ꢟ
ꢞ
ꢙ
ꢧ
ꢞ
ꢜ
ꢧ
ꢪ
ꢞ
ꢟ ꢣ ꢠ ꢟꢘ ꢙꢬ ꢛꢚ ꢞ ꢦꢦ ꢤꢞ ꢜ ꢞ ꢝ ꢣ ꢟ ꢣ ꢜ ꢠ ꢈ  
ꢜ
ꢜ
ꢞ
ꢙ
ꢟ
ꢫ
ꢈ
ꢋ
ꢜ
ꢛ
ꢧ
ꢢ
ꢡ
ꢟ
ꢘ
ꢛ
ꢙ
ꢤ
ꢜ
ꢛ
ꢡ
ꢣ
ꢠ
ꢠ
ꢘ
ꢙ
ꢬ
ꢧ
ꢛ
ꢣ
ꢠ
ꢙ
ꢛ
ꢟ
ꢙ
ꢣ
ꢡ
ꢣ
ꢠ
ꢠ
ꢞ
ꢜ
ꢘ
ꢦ
ꢫ
ꢘ
ꢙ
ꢡ
ꢦ
ꢢ
ꢧ
ꢣ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...13

中文翻译

下载PDF

与CDC2509A_15相关器件

型号 品牌 获取价格 描述 数据表
CDC2509APWLE ETC

获取价格

 		Nine Distributed-Output Clock Driver
CDC2509APWR TI

获取价格

 		3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDC2509APWRG4 TI

获取价格

 		3.3-V Phase-Lock Loop Clock Driver With 3-State Outputs 24-TSSOP 0 to 70
CDC2509B TI

获取价格

 		3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDC2509BPW TI

获取价格

 		3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDC2509BPWG4 TI

获取价格

 		3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDC2509BPWLE ETC

获取价格

 		Nine Distributed-Output Clock Driver
CDC2509BPWR TI

获取价格

 		3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDC2509BPWRG4 TI

获取价格

 		3.3-V PHASE-LOCK LOOP CLOCK DRIVER
CDC2509C TI

获取价格

 		3.3-V PHASE-LOCK LOOP CLOCK DRIVER

与CDC2509A_15相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证