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CDC2351QDWR PDF预览

CDC2351QDWR

更新时间： 2024-11-17 13:06:43
品牌 Logo 应用领域
德州仪器 - TI 时钟驱动器输出元件
页数 文件大小 规格书
7页 110K
描述
LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24, PLASTIC, SO-24

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CDC2351QDWR 技术参数

生命周期：Obsolete零件包装代码：SOIC
包装说明：SOP,针数：24
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.67输入调节：STANDARD
JESD-30 代码：R-PDSO-G24长度：15.4 mm
逻辑集成电路类型：LOW SKEW CLOCK DRIVER功能数量：1
反相输出次数：端子数量：24
实输出次数：10最高工作温度：125 °C
最低工作温度：-40 °C输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
传播延迟（tpd）：11 ns认证状态：Not Qualified
Same Edge Skew-Max（tskwd）：2.5 ns座面最大高度：2.65 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：BICMOS温度等级：AUTOMOTIVE
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL宽度：7.5 mm
Base Number Matches：1

CDC2351QDWR 数据手册

 浏览型号CDC2351QDWR的Datasheet PDF文件第2页浏览型号CDC2351QDWR的Datasheet PDF文件第3页浏览型号CDC2351QDWR的Datasheet PDF文件第4页浏览型号CDC2351QDWR的Datasheet PDF文件第5页浏览型号CDC2351QDWR的Datasheet PDF文件第6页浏览型号CDC2351QDWR的Datasheet PDF文件第7页 
CDC2351  
1-LINE TO 10-LINE CLOCK DRIVER  
WITH 3-STATE OUTPUTS  
SCAS442B – FEBRUARY 1994 – REVISED NOVEMBER 1995  
DB OR DW PACKAGE  
(TOP VIEW)  
Low Output Skew, Low Pulse Skew for  
Clock-Distribution and Clock-Generation  
Applications  
GND  
Y10  
GND  
23 Y1  
1
24  
Operates at 3.3-V V  
CC  
2
LVTTL-Compatible Inputs and Outputs  
V
3
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
V
Y2  
GND  
Y3  
Y4  
GND  
Y5  
V
Y6  
GND  
CC  
Y9  
CC  
4
Supports Mixed-Mode Signal Operation  
(5-V Input and Output Voltages With 3.3-V  
5
OE  
A
6
V
)
CC  
7
P0  
P1  
Y8  
Distributes One Clock Input to Ten Outputs  
8
Outputs Have Internal Series Damping  
Resistor to Reduce Transmission Line  
Effects  
9
10  
11  
12  
V
CC  
Y7  
CC  
Distributed V  
Switching Noise  
and Ground Pins Reduce  
CC  
GND  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
Package Options Include Plastic  
Small-Outline (DW) and Shrink  
Small-Outline (DB) Packages  
description  
The CDC2351 is a high-performance clock-driver circuit that distributes one input (A) to ten outputs (Y) with  
minimum skew for clock distribution. The output-enable (OE) input disables the outputs to a high-impedance  
state. Each output has an internal series damping resistor to improve signal integrity at the load. The CDC2351  
operates at nominal 3.3-V V  
.
CC  
The propagation delays are adjusted at the factory using the P0 and P1 pins. The factory adjustments ensure  
that the part-to-part skew is minimized and is kept within a specified window. Pins P0 and P1 are not intended  
for customer use and should be connected to GND.  
The CDC2351 is characterized for operation from 0°C to 70°C.  
FUNCTION TABLE  
INPUTS  
OUTPUTS  
Yn  
A
OE  
H
L
H
L
Z
Z
L
H
L
H
L
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC-ΙΙΒ is a trademark of Texas Instruments Incorporated.  
Copyright 1995, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567

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