Datasheet > BUK7575-55

BUK7575-55

更新时间： 2024-11-25 22:50:23

品牌	Logo	应用领域
恩智浦 - NXP		晶体晶体管
页数	文件大小	规格书
8页	67K
描述
TrenchMOS transistor Standard level FET

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BUK7575-55 数据手册

Philips Semiconductors

Product specification

TrenchMOS transistor

Standard level FET

BUK7575-55

GENERAL DESCRIPTION

QUICK REFERENCE DATA

N-channel enhancement mode

standard level field-effect power

transistor in a plastic envelope using

’trench’ technology. The device

features very low on-state resistance

and has integral zener diodes giving

ESD protection up to 2kV. It is

intended for use in automotive and

SYMBOL

PARAMETER

MAX.

UNIT

V_DS

I_D

P_tot

T_j

Drain-source voltage

Drain current (DC)

Total power dissipation

Junction temperature

Drain-source on-state

19.7

175

˚C

mΩ

R_DS(ON)

resistance

V_GS= 10 V

general

purpose

switching

applications.

PINNING - TO220AB

PIN CONFIGURATION

SYMBOL

DESCRIPTION

tab

gate

drain

source

tab drain

1 2 3

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V_DS

V_DGR

±V_GS

I_D

I_DM

Drain-source voltage

Drain-gate voltage

Gate-source voltage

Drain current (DC)

19.7

13.9

˚C

R_GS= 20 kΩ

T_mb= 25 ˚C

T_mb= 100 ˚C

T_mb= 25 ˚C

Drain current (DC)

Drain current (pulse peak value)

Total power dissipation

Storage & operating temperature

P_tot

T_stg, T_j

175

- 55

ESD LIMITING VALUE

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V_C

Electrostatic discharge capacitor

voltage, all pins

Human body model

(100 pF, 1.5 kΩ)

THERMAL RESISTANCES

SYMBOL PARAMETER

CONDITIONS

TYP.

MAX.

UNIT

R_{th j-mb}

Thermal resistance junction to

mounting base

2.46

K/W

R_{th j-a}

Thermal resistance junction to

ambient

in free air

K/W

April 1998

Rev 1.100

12 3 4 5 6 7 8

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