9ZX21901C DATASHEET
Electrical Characteristics – Skew and Differential Jitter Parameters
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
tSPO_PLL
CONDITIONS
Input-to-Output Skew in PLL mode
nominal value @ 25°C, 3.3V
MIN
-100
TYP MAX UNITS
NOTES
CLK_IN, DIF[x:0]
0
3.5
0
100
4.5
50
ps
ns
ps
1,2,4,5,8
Input-to-Output Skew in Bypass mode
nominal value @ 25°C, 3.3V
Input-to-Output Skew Varation in PLL mode
across voltage and temperature
CLK_IN, DIF[x:0]
CLK_IN, DIF[x:0]
tPD_BYP
2.5
-50
1,2,3,5,8
1,2,3,5,8
tDSPO_PLL
Input-to-Output Skew Varation in Bypass mode
across voltage and temperature
CLK_IN, DIF[x:0]
CLK_IN, DIF[x:0]
CLK_IN, DIF[x:0]
DIF{x:0]
tDSPO_BYP
-250
250
5
ps
1,2,3,5,8
1,2,3,5,8
1,2,3,5,8
1,2,3,8
Random Differential Tracking error beween two
9ZX devices in Hi BW Mode
ps
(rms)
tDTE
3
Random Differential Spread Spectrum Tracking
error beween two 9ZX devices in Hi BW Mode
tDSSTE
15
37
75
65
ps
Output-to-Output Skew across all outputs
(Common to Bypass and PLL mode)
LOBW#_BYPASS_HIBW = 1
tSKEW_ALL
ps
PLL Jitter Peaking
PLL Jitter Peaking
PLL Bandwidth
PLL Bandwidth
Duty Cycle
jpeak-hibw
jpeak-lobw
pllHIBW
pllLOBW
tDC
0
0
1.3
0.8
3
2.5
2
dB
dB
7,8
7,8
8,9
8,9
1
LOBW#_BYPASS_HIBW = 0
LOBW#_BYPASS_HIBW = 1
LOBW#_BYPASS_HIBW = 0
2
4
MHz
MHz
%
0.7
45
1.1
50
1.4
55
Measured differentially, PLL Mode
Measured differentially, Bypass Mode
@100MHz
Duty Cycle Distortion
Jitter, Cycle to cycle
tDCD
-2
0
2
%
1,10
PLL mode
Additive Jitter in Bypass Mode
41
20
50
50
ps
ps
1,11
1,11
tjcyc-cyc
Notes for preceding table:
1
Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input.
Measured from differential cross-point to differential cross-point. This parameter can be tuned with external feedback path, if present.
2
3
All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it.
4 This parameter is deterministic for a given device
5
Measured with scope averaging on to find mean value. DIF_IN slew rate must be matched to DIF output slew rate.
6.t is the period of the input clock
7 Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking.
8.
Guaranteed by design and characterization, not 100% tested in production.
9
Measured at 3 db down or half power point.
10 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.
11 Measured from differential waveform
19-OUTPUT DIFFERENTIAL ZBUFFER FOR PCIE GEN2/3 AND QPI
8
REVISION N 11/19/15