Datasheet > 9ZX21901C

9ZX21901C

更新时间： 2023-12-20 18:46:01

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
21页	508K
描述
19-output DB1900Z Compliant Buffer

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9ZX21901C 数据手册

9ZX21901C DATASHEET

Electrical Characteristics – Skew and Differential Jitter Parameters

TA = T_COM;Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions

PARAMETER

SYMBOL

t_{SPO_PLL}

CONDITIONS

Input-to-Output Skew in PLL mode

nominal value @ 25°C, 3.3V

MIN

-100

TYP MAX UNITS

NOTES

CLK_IN, DIF[x:0]

3.5

100

4.5

1,2,4,5,8

Input-to-Output Skew in Bypass mode

nominal value @ 25°C, 3.3V

Input-to-Output Skew Varation in PLL mode

across voltage and temperature

CLK_IN, DIF[x:0]

t_{PD_BYP}

2.5

-50

1,2,3,5,8

t_{DSPO_PLL}

Input-to-Output Skew Varation in Bypass mode

across voltage and temperature

CLK_IN, DIF[x:0]

DIF{x:0]

t_{DSPO_BYP}

-250

250

1,2,3,5,8

1,2,3,8

Random Differential Tracking error beween two

9ZX devices in Hi BW Mode

(rms)

t_DTE

Random Differential Spread Spectrum Tracking

error beween two 9ZX devices in Hi BW Mode

t_DSSTE

Output-to-Output Skew across all outputs

(Common to Bypass and PLL mode)

LOBW#_BYPASS_HIBW = 1

t_{SKEW_ALL}

PLL Jitter Peaking

PLL Bandwidth

Duty Cycle

j_peak-hibw

j_peak-lobw

pll_HIBW

pll_LOBW

t_DC

1.3

0.8

2.5

7,8

8,9

LOBW#_BYPASS_HIBW = 0

LOBW#_BYPASS_HIBW = 1

LOBW#_BYPASS_HIBW = 0

MHz

0.7

1.1

1.4

Measured differentially, PLL Mode

Measured differentially, Bypass Mode

@100MHz

Duty Cycle Distortion

Jitter, Cycle to cycle

t_DCD

-2

1,10

PLL mode

Additive Jitter in Bypass Mode

1,11

t_jcyc-cyc

Notes for preceding table:

Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input.

Measured from differential cross-point to differential cross-point. This parameter can be tuned with external feedback path, if present.

All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it.

⁴This parameter is deterministic for a given device

Measured with scope averaging on to find mean value. DIF_IN slew rate must be matched to DIF output slew rate.

^6.t is the period of the input clock

⁷Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking.

Guaranteed by design and characterization, not 100% tested in production.

Measured at 3 db down or half power point.

¹⁰Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.

¹¹Measured from differential waveform

19-OUTPUT DIFFERENTIAL ZBUFFER FOR PCIE GEN2/3 AND QPI

REVISION N 11/19/15

1...5 6 789 10 11...21

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