19-Output DB1900Z for PCIe Gen1-4 and
QPI/UPI
9ZX21901D
DATASHEET
Description
Features
The 9ZX21901D is a second generation DB1900Z differential
buffer for Intel Purley and newer platforms. The part is
backwards compatible to the 9ZX21901C while offering much
improved phase jitter performance. A fixed external feedback
maintains low drift for critical QPI/UPI applications. In bypass
mode, the 9ZX21901D can provide outputs up to 400MHz.
• Fixed feedback path; 0ps input-to-output delay
• 9 Selectable SMBus addresses; multiple devices can share
same SMBus segment
• 8 dedicated OE# pins; hardware control of outputs
• PLL or bypass mode; PLL can dejitter incoming clock
• Selectable PLL BW; minimizes jitter peaking in downstream
PLL's
PCIe Clocking Architectures Supported
• Common Clocked (CC)
• Separate Reference No Spread (SRNS)
• Separate Reference Independent Spread (SRIS)
• Hardware or software control of PLL operating mode;
change mode with software mode does not need power
cycle
• Spread spectrum compatible; tracks spreading input clock
for EMI reduction
Typical Applications
• Servers, Storage, Networking
• SMBus Interface; unused outputs can be disabled
• 100MHz and 133.33MHz PLL mode; legacy QPI support
• 72-QFN 10 x 10 mm package; small board footprint
Output Features
• 19 HCSL output pairs
Key Specifications
• Cycle-to-cycle jitter: < 50ps
• Output-to-output skew: < 50ps
• Input-to-output delay: Fixed at 0 ps
• Input-to-output delay variation: < 50ps
• Phase jitter: PCIe Gen4 < 0.5ps rms
• Phase jitter: UPI 9.6GB/s < 0.1ps rms
Functional Block Diagram
Low Phase
Noise Z-PLL
(SS-
DFB_OUT
DIF[18]
DIF_IN
Compatible)
OE(12:5)#
Bypass path
HIBW_BYPM_LOBW#
100M_133M#
19 outputs
CKPWRGD/PD#
SMB_A0_tri
SMB_A1_tri
SMBDAT
SMBCLK
DIF[0]
IREF
9ZX21901D APRIL 17, 2018
1
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