Datasheet > 9ZXL0652E

9ZXL0652E

更新时间： 2022-02-26 10:53:48

品牌	Logo	应用领域
艾迪悌 - IDT		PC
页数	文件大小	规格书
20页	302K
描述
6-Output DB800ZL Derivat ive for PCIe Gen1â4 and UPI

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9ZXL0652E 数据手册

6-Output DB800ZL Derivative for

PCIe Gen1–4 and UPI with Write

Lock

9ZXL0632E / 9ZXL0652E

Datasheet

Description

Features

▪ SMBus write lock feature; increases system security

▪ LP-HCSL outputs; eliminate 12 resistors, save 20mm²of area

The 9ZXL0632E / 9ZXL0652E second-generation,

enhanced-performance DB800ZL differential buffers. The parts

are functionally compatible to the 9ZXL0632A and 9ZXL0652A

while offering much improved phase jitter performance. A fixed

external feedback maintains low drift for critical QPI/UPI

applications. The 9ZXL0632E and 9ZXL0652E have an SMBus

Write Lockout pin for increased device and system security.

(0632E)

▪ LP-HCSL outputs with 85Ω Zout; eliminate 24 resistors, save

48mm²of area (0652E)

▪ 6 OE# pins; hardware control of each output

▪ Selectable PLL BW; minimizes jitter peaking in cascaded PLL

topologies

PCIe Clocking Architectures

Supported

▪ Hardware/SMBus control of PLL bandwidth and bypass;

change mode without power cycle

▪ Common Clocked (CC)

▪ Spread spectrum compatible; tracks spreading input clock for

EMI reduction

▪ Independent Reference (IR) with and without spread spectrum

▪ 100MHz PLL mode; UPI support

▪ 5 × 5 mm 40-QFN package; small board footprint

Typical Applications

▪ Servers

▪ Storage

▪ JBOD

Key Specifications

▪ Cycle-to-cycle jitter < 50ps

▪ Output-to-output skew < 50 ps

▪ Networking

▪ Input-to-output delay: Fixed at 0ps

▪ Input-to-output delay variation < 50ps

▪ Phase jitter: PCIe Gen4 < 0.5ps rms

▪ Phase jitter: QPI/UPI > = 9.6GB/s < 0.2ps rms

▪ Phase jitter: IF-UPI < 1.0ps rms

Output Features

▪ 6 Low-power HCSL (LP-HCSL) output pairs (0632E)

▪ 6 Low-power HCSL (LP-HCSL) output pairs with 85Ω Zout

(0652E)

Block Diagram

VDDR

VDDA

VDD x9

FBOUT_NC#

FBOUT_NC

PLL

DIFIN#

DIF5#

DIF5

DIFIN

vSMB_WRTLOCK

6 outputs

SMBus

Engine Configuration

Factory

SMBCLK

SMBDAT

DIF0#

DIF0

^vHIBW_BYPM-LOBW#

^CKPWRGD_PD#

vOE[5:0]#

Control Logic

Resistors are integrated on 9ZXL065x

devices and external on9ZXL063x devices

GNDR

EPAD/GND

August 14, 2018

12 3 4 5 6 7...20

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