9ZXL0632E / 9ZXL0652E Datasheet
PLL Operating Mode Readback Table
HiBW_BypM_LoBW#
Byte0, bit 7
Byte 0, bit 6
Low (Low BW)
Mid (Bypass)
0
0
1
0
1
1
High (High BW)
Pow er Connections
Pin Number
V
GND
Description
DD
40
41
4
Analog PLL
Analog input
DIF clocks
5
12,16,20,21,25,29,31,35,39
41
Pin Descriptions
Table 1. Pin Descriptions
Number
Name
Type
Description
1
This pin prevents SMBus writes when asserted. SMBus reads are not affected. This pin has
an internal 120kΩ pull-down.
vSMB_WRTLOCK
Input
0 = SMBus writes allows, 1 = SMBus writes blocked.
2
3
Latched Tri-level input to select High BW, Bypass or Low BW Mode. Has an internal 120kΩ pull-up
^HIBW_BYPM_LOBW#
^CKPWRGD_PD#
In
resistor. See PLL Operating Mode table for details.
Input notifies device to sample latched inputs and start up on first high assertion. Low
enters Power Down Mode, subsequent high assertions exit Power Down Mode. This pin
has internal 120kΩ pull-up resistor.
Input
4
5
GND
GND
Ground pin.
Power supply for differential input clock (receiver). This V should be treated as an analog
power rail and filtered appropriately. Nominally 3.3V.
DD
VDDR
Power
6
7
DIF_IN
DIF_IN#
SMBDAT
SMBCLK
Input
Input
I/O
HCSL true input.
HCSL complementary input.
8
Data pin of SMBUS circuitry.
9
Input
Clock pin of SMBUS circuitry.
10
Complementary half of differential feedback output. This pin should NOT be connected to
FBOUT_NC#
Output anything outside the chip. It exists to provide delay path matching to get 0 propagation
delay.
11
True half of differential feedback output. This pin should NOT be connected to anything
Output
FBOUT_NC
VDD
outside the chip. It exists to provide delay path matching to get 0 propagation delay.
12
13
14
Power Power supply, nominally 3.3V.
Active low input for enabling output 0. This pin has an internal 120kΩ pull-down.
vOE0#
DIF0
Input
1 = disable outputs, 0 = enable outputs.
Output Differential true clock output.
©2018 Integrated Device Technology, Inc.
4
August 14, 2018