9ZXL0831E / 9ZXL0851E
8-Output DB800ZL for PCIe
Gen1–4 and QPI/UPI
Datasheet
Description
The 9ZXL0831E / 9ZXL0851E are second-generation enhanced
performance DB800ZL differential buffers. The parts are
Features
▪ LP-HCSL outputs; eliminate 16 resistors, save 27mm2 of area
(0831E)
pin-compatible upgrades to the 9ZXL0831A and 9ZXL0851A, while
offering a much improved phase jitter performance. A fixed external
feedback maintains low drift for critical QPI/UPI applications.
▪ LP-HCSL outputs with 85Ω Zout; eliminate 32 resistors, save
64mm2 of area (0851E)
▪ 8 OE# pins; hardware control of each output
▪ Selectable PLL BW; minimizes jitter peaking in cascaded PLL
PCIe Clocking Architectures
Supported
▪ Common Clocked (CC)
topologies
▪ Hardware/SMBus control of PLL bandwidth and bypass; change
mode without power cycle
▪ Independent Reference (IR) with and without spread spectrum
▪ Spread spectrum compatible; tracks spreading input clock for EMI
reduction
Typical Application
▪ Servers
▪ 100MHz & 133.33MHz PLL mode; UPI and legacy QPI support
▪ 6 × 6 mm 48-VFQFPN package; small board footprint
▪ Storage
Key Specifications
▪ Cycle-to-cycle jitter < 50ps
▪ Networking
▪ SSDs
▪ Output-to-output skew < 50ps
Output Features
▪ 8 Low-Power (LP) HCSL output pairs (0831E)
▪ Input-to-output delay: Fixed at 0ps
▪ Input-to-output delay variation < 50ps
▪ Phase jitter: PCIe Gen4 < 0.5ps rms
▪ Phase jitter: QPI/UPI > = 9.6GB/s < 0.2ps rms
▪ Phase jitter: IF-UPI < 1.0ps rms
▪ 8 Low-Power (LP) HCSL output pairs with 85Ω Zout (0851E)
Block Diagram
VDDR
VDDA
VDD x7
FBOUT_NC#
FBOUT_NC
PLL
DIFIN#
DIFIN
DIF7#
DIF7
^100M_133M#
8 outputs
SMBus
Engine Configuration
Factory
SMBCLK
SMBDAT
DIF0#
DIF0
^vHIBW_BYPM-LOBW#
^CKPWRGD_PD#
vOE[7:0]#
Control Logic
Resistors are integrated on 9ZXL085x devices and
external on 9ZXL083x devices
GNDR
EPAD/GND
©2018 Integrated Device Technology, Inc
1
August 14, 2018