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9ZXL1231 PDF预览

9ZXL1231

更新时间: 2023-12-20 18:46:36
品牌 Logo 应用领域
瑞萨 - RENESAS /
页数 文件大小 规格书
19页 382K
描述
DB1200ZL 12-Output Low Power HCSL Buffer

9ZXL1231 数据手册

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12-output DB1200ZL  
9ZXL1231  
DATASHEET  
General Description  
Features/Benefits  
The 9ZXL1231 meets the demanding requirements of the  
Intel DB1200ZL specification, including the critical low-drift  
requirements of Intel CPUs.  
Low-power push-pull HCSL outputs; eliminate 24 resistors,  
2
save 41mm of area  
Pin compatible to 9ZX21201; easy path to >50% power  
savings  
Space-saving 64 VFQFPN package  
Fixed feedback path for 0ps input-to-output delay  
9 Selectable SMBus Addresses; multiple devices can  
share the same SMBus Segment  
Recommended Application  
Buffer for Romley, Grantley and Purley Servers, solid state  
storage and PCIe  
12 OE# pins; hardware control of each output  
PLL or bypass mode; PLL can dejitter incoming clock  
Selectable PLL bandwidth; minimizes jitter peaking in  
downstream PLL's  
Output Features  
12 - Low-Power (LP) HCSL output pairs  
Key Specifications  
Cycle-to-cycle jitter <50ps  
Spread Spectrum Compatible; tracks spreading input clock  
for low EMI  
Output-to-output skew <50 ps  
Input-to-output delay variation <50ps  
PCIe Gen3 phase jitter <1.0ps RMS  
Phase jitter: QPI/UPI >=9.6GB/s <0.2ps rms  
Block Diagram  
OE(11:0)#  
DFB_OUT_NC  
Z-PLL  
(SS Compatible)  
DIF(11:0)  
DIF_IN  
DIF_IN#  
HIBW_BYPM_LOBW#  
100M_133M#  
CKPWRGD/PD#  
SMB_A0_tri  
Logic  
SMB_A1_tri  
SMBDAT  
SMBCLK  
9ZXL1231 REVISION J 05/25/16  

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