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9ZX21901C PDF预览

9ZX21901C

更新时间: 2023-12-20 18:46:01
品牌 Logo 应用领域
瑞萨 - RENESAS /
页数 文件大小 规格书
21页 508K
描述
19-output DB1900Z Compliant Buffer

9ZX21901C 数据手册

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Electrical Characteristics – Absolute Maximum Ratings  
PARAMETER  
SYMBOL  
CONDITIONS  
UNITS NOTES  
MIN  
TYP  
MAX  
4.6  
4.6  
3.3V Core Supply Voltage  
3.3V Logic Supply Voltage  
Input Low Voltage  
VDDA  
VDD  
VIL  
V
V
V
1,2  
1,2  
1
GND-0.5  
Input High Voltage  
Input High Voltage  
VIH  
Except for SMBus interface  
SMBus clock and data pins  
VDD+0.5V  
5.5V  
V
V
°C  
°C  
°C  
V
1
1
VIHSMB  
1
1
1
1
Storage Temperature  
Junction Temperature  
Case Temperature  
Ts  
Tj  
Tc  
-65  
150  
125  
110  
Input ESD protection  
ESD prot  
Human Body Model  
2000  
1Guaranteed by design and characterization, not 100% tested in production.  
2 Operation under these conditions is neither implied nor guaranteed.  
Electrical Characteristics – DIF_IN Clock Input Parameters  
TAMB=TCOM unless otherwise indicated, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS NOTES  
Input Crossover Voltage -  
DIF_IN  
VCROSS  
Cross Over Voltage  
150  
900  
mV  
1
Input Swing - DIF_IN  
Input Slew Rate - DIF_IN  
Input Leakage Current  
Input Duty Cycle  
VSWING  
dv/dt  
IIN  
Differential value  
Measured differentially  
300  
0.4  
-5  
mV  
V/ns  
uA  
1
8
5
1,2  
VIN = VDD , VIN = GND  
dtin  
Measurement from differential wavefrom  
45  
0
55  
125  
%
1
1
Input Jitter - Cycle to Cycle  
JDIFIn  
Differential Measurement  
ps  
1 Guaranteed by design and characterization, not 100% tested in production.  
2Slew rate measured through +/-75mV window centered around differential zero  
Electrical Characteristics – Current Consumption  
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP MAX UNITS  
NOTES  
Operating Supply Current  
Powerdown Current  
IDD3.3OP  
All outputs active @100MHz, CL = Full load;  
All differential pairs tri-stated  
407  
12  
500  
36  
mA  
mA  
1
1
IDD3.3PDZ  
1Guaranteed by design and characterization, not 100% tested in production.  
REVISION N 11/19/15  

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