Datasheet > 9ZX21901C

9ZX21901C

更新时间： 2023-12-20 18:46:01

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
21页	508K
描述
19-output DB1900Z Compliant Buffer

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数据手册

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9ZX21901C 数据手册

9ZX21901C DATASHEET

Pin Configuration

72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55

OE11#

DIF_11#

DIF_11

OE10#

DIF_10#

DIF_10

OE9#

VDDA 1

GNDA 2

IREF 3

100M_133M# 4

HIBW_BYPM_LOBW# 5

CKPWRGD_PD# 6

GND 7

DIF_9#

DIF_9

VDD

VDDR 8

9ZX21901C

DIF_IN 9

NOTE: DFB_OUT pins must be terminated identically

to the regular DIF outputs

DIF_IN# 10

GND

SMB_A0_tri 11

SMBDAT 12

OE8#

DIF_8#

DIF_8

OE7#

SMBCLK 13

SMB_A1_tri 14

DIF_7#

DIF_7

OE6#

DFB_OUT# 17

DFB_OUT 18

19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

72-pin VFQFPN

Functionality at Power Up (PLL Mode)

Power Connections

DIF_IN

(MHz)

100.00

133.33

DIF_x

(MHz)

DIF_IN

Pin Number

100M_133M#

Description

VDD

GND

Analog PLL

Analog Input

21, 31, 45,

58, 68

26, 44, 63

DIF clocks

PLL Operating Mode Readback Table

HiBW_BypM_LoBW#

Low (Low BW)

Byte0, bit 7

Byte 0, bit 6

9ZX21901 SMBus Addressing

Mid (Bypass)

High (High BW)

SMBus Address

(Rd/Wrt bit = 0)

SMB_A1_tri SMB_A0_tri

PLL Operating Mode

HiBW_BypM_LoBW#

Low

MODE

PLL Lo BW

Mid

High

Bypass

PLL Hi BW

NOTE: PLL is OFF in Bypass Mode

Tri-level Input Thresholds

Level

Low

Voltage

<0.8V

Mid

High

1.2<Vin<1.8V

Vin > 2.2V

19-OUTPUT DIFFERENTIAL ZBUFFER FOR PCIE GEN2/3 AND QPI

REVISION N 11/19/15

123 4 5 6 7...21

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