Datasheet > 9ZXL0651

9ZXL0651

更新时间： 2023-12-20 18:44:53

品牌	Logo	应用领域
瑞萨 - RENESAS		PC
页数	文件大小	规格书
15页	628K
描述
6-Output Low-power Buffer for PCIe Gen1-2-3 and QPI with Zo=85 Ohms

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9ZXL0651 数据手册

6-Output DB800ZL Derivative with

Integrated 85ohm Terminations

9ZXL0651

Datasheet

Description

Features

The 9ZXL0651 is a low-power 6-output differential buffer

that meets all the performance requirements of the Intel

DB1200Z specification. It consumes 50% less power than

standard HCSL devices and has internal terminations to

allow direct connection to 85 transmission lines. It is

suitable for PCI-Express Gen1/2/3 or QPI/UPI applications,

and uses a fixed external feedback to maintain low drift for

demanding QPI/UPI applications.

• 25MHz PFT clock delay management

• Low-Power-HCSL outputs with Zo = 85; save power

and board space – no termination resistors required.

Ideal for blade servers.

• Space-saving 40-pin VFQFPN package

• Fixed feedback path for 0ps input-to-output delay

• 6 OE# pins; hardware control of each output

• PLL or bypass mode; PLL can dejitter incoming clock

Applications

Buffer for Romley, Grantley and Purley Servers, SSDs and

PCIe

• Selectable PLL bandwidth; minimizes jitter peaking in

downstream PLLs

• Spread spectrum compatible; tracks spreading input

clock for low EMI

Output Features

• 6 – LP-HCSL Output Pairs w/integrated terminations

(Zo = 85)

Key Specifications

• Cycle-to-cycle jitter < 50ps

• Output-to-output skew < 65ps

• Input-to-output delay variation < 50ps

• PCIe Gen3 phase jitter < 1.0ps RMS

• QPI/UPI 9.6GT/s 12UI phase jitter < 0.2ps RMS

Block Diagram

OE(5:0)#

DFB_OUT_NC

Z-PLL

(SS Compatible)

DIF_IN

DIF_IN#

DIF(5:0)

HIBW_BYPM_LOBW#

CKPWRGD/PD#

Logic

SMBDAT

SMBCLK

January 28, 2021

12 3 4 5 6 7...15

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