6-Output DB800ZL Derivative
for PCIe Gen1–4 and UPI
9ZXL0631E / 9ZXL0651E
Datasheet
Description
Features
▪ LP-HCSL outputs; eliminate 12 resistors, save 20mm2 of area
The 9ZXL0631E / 9ZXL0651E are second-generation,
enhanced-performance DB800ZL derivatives. The parts are
pin-compatible upgrades to the 9ZXL0631A and 9ZXL0651A,
while offering a much improved phase jitter performance. A fixed
external feedback maintains low drift for critical QPI/UPI
applications.
(0631E)
▪ LP-HCSL outputs with 85Ω Zout; eliminate 24 resistors, save
48mm2 of area (0651E)
▪ 6 OE# pins; hardware control of each output
▪ Selectable PLL BW; minimizes jitter peaking in cascaded PLL
topologies
PCIe Clocking Architectures
Supported
▪ Hardware/SMBus control of PLL bandwidth and bypass;
change mode without power cycle
▪ Spread spectrum compatible; tracks spreading input clock for
▪ Common Clocked (CC)
EMI reduction
▪ Independent Reference (IR) with and without spread spectrum
▪ 100MHz PLL Mode; UPI support
▪ 5 × 5 mm 40-QFN package; small board footprint
Typical Applications
▪ Servers
▪ Storage
▪ JBOD
Key Specifications
▪ Cycle-to-cycle jitter < 50ps
▪ Output-to-output skew < 50 ps
▪ Networking
▪ Input-to-output delay: fixed at 0ps
▪ Input-to-output delay variation < 50ps
▪ Phase jitter: PCIe Gen4 < 0.5ps rms
▪ Phase jitter: QPI/UPI > = 9.6GB/s < 0.2ps rms
▪ Phase jitter: IF-UPI < 1.0ps rms
Output Features
▪ 6 Low-power HCSL (LP-HCSL) output pairs (0631E)
▪ 6 Low-power HCSL (LP-HCSL) output pairs with 85Ω Zout
(0651E)
Block Diagram
VDDR
VDDA
VDD x9
FBOUT_NC#
FBOUT_NC
PLL
DIFIN#
DIFIN
DIF5#
DIF5
6 outputs
SMBus
Factory
SMBCLK
SMBDAT
Engine Configuration
DIF0#
DIF0
^vHIBW_BYPM-LOBW#
^CKPWRGD_PD#
vOE[5:0]#
Control Logic
Resistors are integrated on 9ZXL065x
devices and external on9ZXL063x devices
GNDR
EPAD/GND
©2018 Integrated Device Technology, Inc.
1
August 14, 2018