Datasheet > 9ZX21901C

9ZX21901C

更新时间： 2023-12-20 18:46:01

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
21页	508K
描述
19-output DB1900Z Compliant Buffer

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9ZX21901C 数据手册

9ZX21901C DATASHEET

Electrical Characteristics – Input/Supply/Common Parameters

TA = T_COM;Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions

PARAMETER

SYMBOL

T_COM

CONDITIONS

MIN

TYP

MAX

UNITS NOTES

Ambient Operating

Temperature

Commmercial range

°C

Single-ended inputs, except SMBus, low

threshold and tri-level inputs

Single-ended inputs, except SMBus, low

threshold and tri-level inputs

Input High Voltage

Input Low Voltage

V_IH

V_DD+ 0.3

V_IL

I_IN

GND - 0.3

-5

0.8

Single-ended inputs, V_IN= GND, V_IN= VDD

Single-ended inputs

_IN= 0 V; Inputs with internal pull-up resistors

Input Current

I_INP

-200

200

_IN= VDD; Inputs with internal pull-down resistors

F_ibyp

F_ipll

V_DD= 3.3 V, Bypass mode

V_DD= 3.3 V, 100MHz PLL mode

V_DD= 3.3 V, 133.33MHz PLL mode

400

105

140

MHz

Input Frequency

Pin Inductance

Capacitance

100.00

133.33

F_ipll

120

L_pin

C_IN

Logic Inputs, except DIF_IN

DIF_IN differential clock inputs

1.5

C_{INDIF_IN}

2.7

1,4

C_OUT

Output pin capacitance

From V_DDPower-Up and after input clock

stabilization or de-assertion of PD# to 1st clock

Allowable Frequency

Clk Stabilization

T_STAB

1.8

1,2

Input SS Modulation

Frequency

f_MODIN

t_LATOE#

t_DRVPD

kHz

clocks

(Triangular Modulation)

DIF start after OE# assertion

DIF stop after OE# deassertion

DIF output enable after

OE# Latency

Tdrive_PD#

1,3

300

PD# de-assertion

Tfall

t_F

Fall time of control inputs

1,2

Trise

t_R

Rise time of control inputs

SMBus Input Low Voltage

SMBus Input High Voltage

V_ILSMB

V_IHSMB

0.8

2.1

V_DDSMB

0.4

SMBus Output Low Voltage V_OLSMB

@ I_PULLUP

@ V_OL

SMBus Sink Current

Nominal Bus Voltage

SCLK/SDATA Rise Time

I_PULLUP

V_DDSMB

t_RSMB

3V to 5V +/- 10%

2.7

5.5

1000

300

(Max VIL - 0.15) to (Min VIH + 0.15)

(Min VIH + 0.15) to (Max VIL - 0.15)

SCLK/SDATA Fall Time

SMBus Operating

Frequency

t_FSMB

f_MAXSMB

Maximum SMBus operating frequency

100

kHz

1,5

¹Guaranteed by design and characterization, not 100% tested in production.

²Control input must be monotonic from 20% to 80% of input swing.

³Time from deassertion until outputs are >200 mV

⁴DIF_IN input

⁵The differential input clock must be running for the SMBus to be active

19-OUTPUT DIFFERENTIAL ZBUFFER FOR PCIE GEN2/3 AND QPI

REVISION N 11/19/15

1...3 4 567 8 9...21

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