Datasheet > 9ZXL0451E

9ZXL0451E

更新时间： 2023-12-20 18:44:10

品牌	Logo	应用领域
瑞萨 - RENESAS		PC
页数	文件大小	规格书
34页	1350K
描述
4-Output DB800ZL PCIe Zero-Delay/Fanout Clock Buffer

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数据手册

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9ZXL0451E 数据手册

9ZXL04x1E/9ZXL06x1E/

9ZXL08x1E/9ZXL12x1E

4 to 12-Output Buffers for PCIe

Gen1–5 and UPI

Datasheet

Description

Features

▪ 4–12 Low-power HCSL (LP-HCSL) outputs

The 9ZXL04x1E/9ZXL06x1E/9ZXL08x1E/9ZXL12x1E family of

Zero-Delay/Fanout Buffers (ZDB, FOB) are 2nd-generation

enhanced performance buffers for PCIe and CPU applications.

The family meets all published QPI/UPI, DB2000Q and PCIe

Gen1–5 jitter specifications. Devices range from 4 to 12 outputs,

with each output having an OE# pin to support the PCIe

CLKREQ# function for low power states. All devices meet

DB2000Q, DB1200ZL and DB800ZL jitter and skew requirements.

▪ Integrated terminations eliminate up to 4 resistors per output

pair

▪ Dedicated OE# pins support PCIe CLKREQ# function

▪ Up to 9 selectable SMBus addresses (9ZXL12)

▪ Selectable PLL bandwidths minimizes jitter peaking in

cascaded PLL topologies

▪ Hardware/SMBus control of ZDB and FOB modes

▪ Spread-spectrum compatible

PCIe Clocking Architectures

▪ Common Clocked (CC)

▪ 1–400MHz FOB operation (all devices)

▪ Independent Reference (IR) with and without spread spectrum

(SRIS, SRNS)

▪ 100MHz and 133.33MHz ZDB mode (9ZXL12, 9ZXL08)

▪ 100MHz ZDB mode (9ZXL06, 9ZXL04)

▪ -40°C to +85°C operating temperature range (all devices)

▪ -40°C to +105°C operating temperature range (9ZXL08)

▪ Package information: see Ordering Information for details

Key Specifications

▪ Fanout Buffer Mode additive phase jitter:

• PCIe Gen5 CC < 24fs RMS

• DB2000Q additive jitter < 40fs RMS

• QPI/UPI 11.4GB/s < 40fs RMS

• IF-UPI additive jitter < 70fs RMS

▪ ZDB Mode phase jitter:

Applications

▪ Servers/High-performance Computing

▪ nVME Storage

▪ Networking

• PCIe Gen5 CC < 22fs RMS

▪ Accelerators

• QPI/UPI 11.4GB/s < 120fs RMS

• IF-UPI additive jitter < 130fs RMS

▪ Cycle-to-cycle jitter < 50ps

▪ Industrial Control

▪ Output-to-output skew < 50 ps

Block Diagram

VDDIO (9ZXL12x1 only)

VDDR

VDDA

VDD

FBOUT_NC#

FBOUT_NC

PLL

DIF_IN#

DIF_IN

DIFn#

DIFn

9ZXL12x1

9ZXL08x1

only

^100M_133M#

vSADR1_tri

12, 8, 6, or 4

outputs

9ZXL12x1 only

SMBus

Engine Configuration

Factory

vSADR0_tri

SMBCLK

SMBDAT

9ZXL12x1

9ZXL0451

only

DIF0#

DIF0

^vHIBW_BYPM-LOBW#

^CKPWRGD_PD#

vOE[n:0]#

Control Logic

Series resistors are integrated on 9ZXLxx51 devices

and external on 9ZXLxx31 devices

GNDA

GND

December 19, 2022

12 3 4 5 6 7...34

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