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8102403VA PDF预览

8102403VA

更新时间: 2024-01-22 00:18:27
品牌 Logo 应用领域
瑞萨 - RENESAS 静态存储器内存集成电路
页数 文件大小 规格书
8页 92K
描述
4KX1 STANDARD SRAM, 220ns, CDIP18

8102403VA 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP18,.3
针数:18Reach Compliance Code:not_compliant
ECCN代码:3A001.A.2.CHTS代码:8542.32.00.41
风险等级:5.88Is Samacsys:N
最长访问时间:220 nsI/O 类型:SEPARATE
JESD-30 代码:R-GDIP-T18内存密度:4096 bit
内存集成电路类型:STANDARD SRAM内存宽度:1
功能数量:1端子数量:18
字数:4096 words字数代码:4000
工作模式:ASYNCHRONOUS最高工作温度:125 °C
最低工作温度:-55 °C组织:4KX1
输出特性:3-STATE封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装等效代码:DIP18,.3
封装形状:RECTANGULAR封装形式:IN-LINE
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V认证状态:Not Qualified
筛选级别:38535Q/M;38534H;883B座面最大高度:5.08 mm
最大待机电流:0.000025 A最小待机电流:2 V
子类别:SRAMs最大压摆率:0.007 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

8102403VA 数据手册

 浏览型号8102403VA的Datasheet PDF文件第2页浏览型号8102403VA的Datasheet PDF文件第3页浏览型号8102403VA的Datasheet PDF文件第4页浏览型号8102403VA的Datasheet PDF文件第5页浏览型号8102403VA的Datasheet PDF文件第6页浏览型号8102403VA的Datasheet PDF文件第8页 
HM-6504  
state until E returns high (T = 2). For this cycle, the data returns to the high state, the output buffer and all inputs are  
input is latched by E going low; therefore, data set-up and disabled and all signals are unlatched. The device is now  
hold times should be referenced to E. When E (T = 2) ready for the next cycle.  
Timing Waveforms (Continued)  
(7)  
TAVEL  
(8)  
(7)  
TELAX  
TAVEL  
A
E
ADD VALID  
NEXT ADD  
(18) TELEL  
(5) TELEH  
(6)  
TEHEL  
(10)  
(6)  
TEHEL  
TWLEH  
(9)  
TWLWH  
W
(14)  
(16)  
TDVWL  
TWLDX  
DATA VALID  
D
Q
(4)  
TEHQZ  
(3)  
TELQX  
HIGH Z  
HIGH Z  
TIME  
REFERENCE  
-1  
0
1
2
3
4
5
FIGURE 13. LATE WRITE CYCLE  
TRUTH TABLE  
OUTPUTS  
INPUTS  
TIME  
REFERENCE  
E
W
X
A
X
V
X
X
X
X
V
D
X
X
V
X
X
X
X
Q
Z
Z
X
X
X
Z
Z
FUNCTION  
-1  
0
1
2
3
4
5
H
Memory Disabled  
H
Cycle Begins, Addresses are Latched  
Write Begins, Data is Latched  
Write In Progress Internally  
L
L
H
H
X
H
Write Completed  
H
Prepare for Next Cycle (Same as -1)  
Cycle Ends, Next Cycle Begins (Same as 0)  
The late write cycle is a cross between the early write cycle between these two cases. With this cycle the output may  
and the read-modify-write cycle.  
become active, and may become valid data, or may remain  
active but undefined. Valid data is written into the RAM if  
data setup, data hold, write setup and write pulse widths are  
observed.  
Recall that in the early write, the output is guaranteed to  
remain high impedance, and in the read-modify-write the  
output is guaranteed valid at access time. The late write is  
132  

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