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810252AGILF PDF预览

810252AGILF

更新时间: 2024-11-05 01:11:39
品牌 Logo 应用领域
艾迪悌 - IDT 时钟光电二极管外围集成电路石英晶振压控振荡器晶体
页数 文件大小 规格书
16页 257K
描述
VCXO and Synchronous Ethernet Jit ter At tenuator

810252AGILF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP-16针数:16
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.81
其他特性:CAN ALSO OPERATES AT 2.5V SUPPLYJESD-30 代码:R-PDSO-G16
JESD-609代码:e3长度:5 mm
湿度敏感等级:1端子数量:16
最高工作温度:85 °C最低工作温度:-40 °C
最大输出时钟频率:25 MHz封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:2.5/3.3 V
主时钟/晶体标称频率:25 MHz认证状态:Not Qualified
座面最大高度:1.2 mm子类别:Clock Generators
最大压摆率:40 mA最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:4.4 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER
Base Number Matches:1

810252AGILF 数据手册

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VCXO and Synchronous Ethernet  
Jitter Attenuator  
810252I  
Data Sheet  
General Description  
Features  
The 810252I is a high performance, low jitter/low phase noise  
VCXO. The 810252I uses a low frequency and low cost pullable  
crystal to achieve jitter attenuation for synchronous Ethernet  
applications. The 810252I can take an input of 25MHz and produce  
two LVCMOS outputs of 25MHz.  
Two single-ended outputs (LVCMOS or LVTTL levels),  
output Impedance: 15  
Phase jitter attenuation by the VCXO-PLL using a 25MHz pullable  
external crystal (XTAL)  
Input frequencies: 25MHz or 125MHz  
Output frequency: 25MHz  
The device is packaged in a small 16 lead TSSOP package and is  
ideal for use on space constrained boards typically encountered in  
most synchronous ethernet applications.  
PLL loop bandwidth adjustable by external components  
Full 3.3V or 2.5V supply voltage  
-40°C to 85°C ambient operating temperature  
Available in lead-free (RoHS 6) package  
Applications  
Synchronous Ethernet v0.39a  
End equipment compliant with Std IEEE 802.039a  
Pin Assignment  
Block Diagram  
CLK_IN  
VDD  
PLL_SEL  
GND  
Q0  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
(External Loop Filter Inputs)  
LF1  
LF1  
LF0  
PLL_SEL  
OE  
Q1  
VDDO  
OE  
LF0  
GND  
25MHz  
XTAL_IN  
VDDA  
VDD  
10 XTAL_OUT  
GND  
(25MHz or 125MHz  
Input Frequency Auto Detect)  
9
Q0  
810252I  
Pre-  
Divider  
Pulldown  
CLK_IN  
PFD  
CP  
1
0
VCXO  
25MHz  
Q1  
16-Lead TSSOP  
4.4mm x 5.0mm x 0.925mm  
package body  
(÷1 or ÷5)  
VCXO-PLL  
G Package  
Top View  
©2016 Integrated Device Technology, Inc  
1
Revision B March 3, 2016  

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