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810252BKI-02LF PDF预览

810252BKI-02LF

更新时间： 2024-11-20 14:49:11
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
19页 4578K
描述
PLL Based Clock Driver, 810252 Series, 2 True Output(s), 0 Inverted Output(s), 5 X 5 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-220VHHD-2, VFQFN-32

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810252BKI-02LF 技术参数

是否Rohs认证：符合生命周期：Obsolete
零件包装代码：QFN包装说明：5 X 5 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-220VHHD-2, VFQFN-32
针数：32Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.8Is Samacsys：N
系列：810252输入调节：DIFFERENTIAL MUX
JESD-30 代码：S-XQCC-N32JESD-609代码：e3
长度：5 mm逻辑集成电路类型：PLL BASED CLOCK DRIVER
功能数量：1反相输出次数：
端子数量：32实输出次数：2
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：UNSPECIFIED封装代码：HVQCCN
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：260认证状态：Not Qualified
Same Edge Skew-Max（tskwd）：0.2 ns座面最大高度：1 mm
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
温度等级：INDUSTRIAL端子面层：MATTE TIN
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：5 mm最小 fmax：312.5 MHz
Base Number Matches：1

810252BKI-02LF 数据手册

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VCXO JITTER ATTENUATOR &  
FEMTOCLOCK™ MULTIPLIER  
ICS810252I-02  
GENERAL DESCRIPTION  
FEATURES  
• Two LVCMOS/LVTTL outputs, 14Ω output impedance  
Each output supports independent frequency selection at  
25MHz, 125MHz, 156.25MHz and 312.5MHz  
The ICS810252I-02 is  
a member of the  
ICS  
HiperClockS™family of high performance clock  
solutions from IDT. The ICS810252I-02 is a PLL  
based synchronous multiplier that is optimized for  
PDH or SONET to Ethernet clock jitter attenuation  
HiPerClockS™  
• Two differential inputs support the following input types:  
LVPECL, LVDS, LVHSTL, SSTL, HCSL  
and frequency translation. The device contains two internal  
frequency multiplication stages that are cascaded in series.  
The first stage is a VCXO PLL that is optimized to provide  
reference clock jitter attenuation. The second stage is a  
FemtoClock™ frequency multiplier that provides the low jitter,  
high frequency Ethernet output clock that easily meets Gigabit  
and 10 Gigabit Ethernet jitter requirements. Pre-divider and  
output divider multiplication ratios are selected using device  
selection control pins. The multiplication ratios are optimized  
to support most common clock rates used in PDH, SONET  
and Ethernet applications. The VCXO requires the use of an  
external, inexpensive pullable crystal. The VCXO uses external  
passive loop filter components which allows configuration of  
the PLL loop bandwidth and damping characteristics. The  
device is packaged in a space-saving 32-VFQFN package and  
supports industrial temperature range.  
• Accepts input frequencies from 8kHz to 155.52MHz including  
8kHz, 1.544MHz, 2.048MHz, 19.44MHz, 25MHz, 77.76MHz,  
125MHz and 155.52MHz  
• Attenuates the phase jitter of the input clock by using a low-  
cost pullable fundamental mode VCXO crystal  
• VCXO PLL bandwidth can be optimized for jitter attenuation  
and reference tracking using external loop filter connection  
• FemtoClock frequency multiplier provides low jitter, high  
frequency output  
• Absolute pull range: 50ppm  
• FemtoClock VCO frequency: 625MHz  
• RMS phase jitter @ 125MHz, using a 25MHz crystal  
(10kHz – 20MHz): 1.3ps  
• 3.3V supply voltage  
• -40°C to 85°C ambient operating temperature  
• Available in both standard (RoHS 5) and lead-free (RoHS 6)  
packages  
PIN ASSIGNMENT  
32 31 30 29 28 27 26 25  
1
2
3
4
5
6
7
8
LF1  
LF0  
24  
23  
22  
21  
20  
19  
18  
17  
GND  
nc  
ISET  
QB  
GND  
VDDO  
nc  
ICS810252I-02  
CLK_SEL  
VDD  
QA  
RESERVED  
GND  
GND  
ODASEL_0  
9
10 11 12 13 14 15 16  
32-Lead VFQFN  
5mm x 5mm x 0.925 package body  
K Package  
Top View  
IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER  
1
ICS810252BKI-02 REV. A OCTOBER 22,2008  
1234567...19

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