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810252BKI-03LF

更新时间： 2024-11-04 06:32:43
品牌 Logo 应用领域
艾迪悌 - IDT 石英晶振压控振荡器衰减器
页数 文件大小 规格书
24页 212K
描述
VCXO Jitter Attenuator and FemtoClock™ Multiplier

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810252BKI-03LF 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：VFQFPN
包装说明：VFQFN-32针数：32
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.82
JESD-30 代码：S-XQCC-N32JESD-609代码：e3
长度：5 mm湿度敏感等级：3
功能数量：1端子数量：32
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：UNSPECIFIED封装代码：HVQCCN
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：260座面最大高度：1 mm
标称供电电压：3.3 V表面贴装：YES
电信集成电路类型：PCM JITTER ATTENUATOR温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn) - annealed端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：5 mm
Base Number Matches：1

810252BKI-03LF 数据手册

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VCXO Jitter Attenuator and  
FemtoClock™ Multiplier  
ICS810252BI-03  
DATA SHEET  
GENERAL DESCRIPTION  
FEATURES  
• Two LVCMOS/LVTTL outputs, 17Ω impedance  
Each output supports independent frequency selection at  
25MHz, 62.5MHz, 125MHz, and 156.25MHz  
The ICS810252BI-03 is a member of the  
ICS  
HiperClockS™ family of high performance clock  
solutions from IDT. The ICS810252BI-03 is a PLL  
based synchronous multiplier that is optimized for  
PDH or SONET to Ethernet clock jitter attenuation  
HiPerClockS™  
• Two differential inputs support the following input types:  
LVPECL, LVDS, LVHSTL, SSTL, HCSL  
and frequency translation. The device contains two internal  
frequency multiplication stages that are cascaded in series.  
The first stage is a VCXO PLL that is optimized to provide  
reference clock jitter attenuation. The second stage is a  
FemtoClock™ frequency multiplier that provides the low jitter,  
high frequency Ethernet output clock that easily meets Gigabit  
and 10 Gigabit Ethernet jitter requirements. Pre-divider and  
output divider multiplication ratios are selected using device  
selection control pins. The multiplication ratios are optimized  
to support most common clock rates used in PDH, SONET  
and Ethernet applications. The VCXO requires the use of an  
external, inexpensive pullable crystal. The VCXO uses external  
passive loop filter components which allows configuration of  
the PLL loop bandwidth and damping characteristics. The  
device is packaged in a space-saving 32-TQFP, E-Pad and 32-  
VFQFN packages and supports industrial temperature range.  
• Accepts input frequencies from 8kHz to 155.52MHz including  
8kHz, 1.544MHz, 2.048MHz, 19.44MHz, 25MHz, 77.76MHz,  
125MHz and 155.52MHz  
• Attenuates the phase jitter of the input clock by using a low-  
cost pullable fundamental mode VCXO crystal  
• VCXO PLL bandwidth can be optimized for jitter attenuation  
and reference tracking using external loop filter connection  
• FemtoClock frequency multiplier provides low jitter, high  
frequency output  
• Absolute pull range: 50ppm  
• FemtoClock VCO frequency: 625MHz  
• RMS phase jitter @ 125MHz, using a 25MHz crystal  
(12kHz - 20MHz): 1.1ps (typical)  
• 3.3V supply voltage  
• -40°C to 85°C ambient operating temperature  
• Available in lead-free (RoHS 6) package  
PIN ASSIGNMENT  
32 31 30 29 28 27 26 25  
1
2
3
4
5
6
LF1  
LF0  
GND  
24  
23  
22  
21  
20  
19  
18  
17  
VDDO_QB  
QB  
ISET  
GND  
GND  
ICS810252BI-03  
CLK_SEL  
VDD  
VDDO_QA  
QA  
RESERVED  
GND  
7
8
GND  
ODASEL_0  
9 10 11 12 13 14 15 16  
32-Lead TQFP, E-Pad  
7mm x 7mm x 1.0mm package body  
Y package  
Top View  
32-Lead VFQFN  
5mm x 5mm x 0.925mm package body  
K Package  
Top View  
ICS810252BYI-03 REVISION A AUGUST 20, 2009  
1
©2009 Integrated Device Technology, Inc.  
1234567...24

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