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8102406VA

更新时间: 2024-11-19 22:23:47
品牌 Logo 应用领域
英特矽尔 - INTERSIL 内存集成电路静态存储器
页数 文件大小 规格书
7页 44K
描述
1024 x 4 CMOS RAM

8102406VA 数据手册

 浏览型号8102406VA的Datasheet PDF文件第2页浏览型号8102406VA的Datasheet PDF文件第3页浏览型号8102406VA的Datasheet PDF文件第4页浏览型号8102406VA的Datasheet PDF文件第5页浏览型号8102406VA的Datasheet PDF文件第6页浏览型号8102406VA的Datasheet PDF文件第7页 
HM-6514  
1024 x 4 CMOS RAM  
March 1997  
Features  
Description  
• Low Power Standby. . . . . . . . . . . . . . . . . . . 125µW Max The HM-6514 is a 1024 x 4 static CMOS RAM fabricated  
using self-aligned silicon gate technology. The device utilizes  
synchronous circuitry to achieve high performance and low  
• Low Power Operation . . . . . . . . . . . . . 35mW/MHz Max  
power operation.  
• Data Retention . . . . . . . . . . . . . . . . . . . . . . . at 2.0V Min  
• TTL Compatible Input/Output  
On-chip latches are provided for addresses allowing efficient  
interfacing with microprocessor systems. The data output  
can be forced to a high impedance state for use in expanded  
memory arrays.  
• Common Data Input/Output  
• Three-State Output  
Gated inputs allow lower operating current and also elimi-  
nate the need for pull up or pull down resistors. The  
HM-6514 is a fully static RAM and may be maintained in any  
state for an indefinite period of time.  
• Standard JEDEC Pinout  
• Fast Access Time. . . . . . . . . . . . . . . . . . 120/200ns Max  
• 18 Pin Package for High Density  
• On-Chip Address Register  
Data retention supply voltage and supply current are guaran-  
teed over temperature.  
• Gated Inputs - No Pull Up or Pull Down Resistors  
Required  
Ordering Information  
120ns  
HM3-6514S-9  
HM1-6514S-9  
24502BVA  
8102402VA  
-
200ns  
300ns  
HM3-6514-9  
HM1-6514-9  
-
TEMPERATURE RANGE  
PACKAGE  
PDIP  
PKG. NO.  
E18.3  
o
o
HM3-6514B-9  
-40 C to +85 C  
o
o
HM1-6514B-9  
-40 C to +85 C  
CERDIP  
JAN#  
F18.3  
F18.3  
F18.3  
J18.B  
J18.B  
-
-
-
8102404VA  
8102406VA  
-
SMD#  
CLCC  
o
o
-
-
-40 C to +85 C  
o
o
-
HM4-6514-B  
-55 C to +125 C  
Pinouts  
HM-6514 (PDIP, CERDIP)  
HM-6514 (CLCC)  
TOP VIEW  
TOP VIEW  
PIN  
A
DESCRIPTION  
1
2
3
4
5
6
7
8
9
18  
17  
16  
15  
14  
13  
12  
11  
10  
A6  
A5  
V
CC  
2
1
18 17  
A7  
Address Input  
Chip Enable  
Write Enable  
Data Input  
16  
A8  
3
4
5
6
7
A4  
A3  
A0  
A1  
A2  
A4  
A8  
E
15 A9  
A3  
A9  
W
D
A0  
DQ0  
DQ1  
DQ2  
DQ3  
W
14 DQ0  
A1  
13  
12  
DQ1  
DQ2  
A2  
Q
Data Output  
E
8
9
10 11  
GND  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
File Number 2995.1  
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 19996-1  

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