TM
HM-6504
March 1997
4096 x 1 CMOS RAM
Features
Description
• Low Power Standby. . . . . . . . . . . . . . . . . . . 125µW Max The HM-6504 is a 4096 x 1 static CMOS RAM fabricated
using self-aligned silicon gate technology. The device uti-
lizes synchronous circuitry to achieve high performance and
• Low Power Operation . . . . . . . . . . . . . .35mW/MHz Max
low power operation.
• Data Retention . . . . . . . . . . . . . . . . . . . . . . . at 2.0V Min
• TTL Compatible Input/Output
On-chip latches are provided for addresses, data input and
data output allowing efficient interfacing with microprocessor
systems. The data output can be forced to a high impedance
state for use in expanded memory arrays.
• Three-State Output
• Standard JEDEC Pinout
• Fast Access Time . . . . . . . . . . . . . . . . . 120/200ns Max
• 18 Lead Package for High Density
• On-Chip Address Register
Gated inputs allow lower operating current and also elimi-
nate the need for pull up or pull down resistors. The
HM-6504 is a fully static RAM and may be maintained in any
state for an indefinite period of time.
• Gated Inputs - No Pull Up or Pull Down Resistors
Required
Data retention supply voltage and supply current are guaran-
teed over temperature.
Ordering Information
120ns
200ns
300ns
HM3-6504-9
HM1-6504-9
-
TEMP. RANGE
PACKAGE
PKG. NO.
E18.3
o
o
-
HM1-6504S-9
24501BVA
810240IVA
-
HM3-6504B-9
-40 C to +85 C
PDIP
o
o
HM1-6504B-9
-40 C to +85 C
CERDIP
JAN #
F18.3
-
-
-
F18.3
8102403VA
-
8102405VA
HM4-6504-9
SMD #
CLCC
F18.3
o
o
-40 C to+85 C
J18.B
Pinouts
HM-6504 (PDIP, CERDIP)
HM-6504 (CLCC)
TOP VIEW
TOP VIEW
PIN
DESCRIPTION
Address Input
Chip Enable
Write Enable
Data Input
A
E
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
A0
A1
A2
A3
A4
A5
Q
V
CC
2
1
18 17
A6
A7
A8
A9
A10
A11
D
16
A7
3
4
5
6
7
A2
A3
A4
A5
Q
W
D
Q
15 A8
14 A9
Data Output
13
12
A10
A11
W
8
9
10 11
GND
E
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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FN2994.1
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