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8102403VA

更新时间: 2024-11-04 20:25:51
品牌 Logo 应用领域
瑞萨 - RENESAS 静态存储器内存集成电路
页数 文件大小 规格书
8页 92K
描述
4KX1 STANDARD SRAM, 220ns, CDIP18

8102403VA 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:DIP包装说明:,
针数:18Reach Compliance Code:not_compliant
ECCN代码:3A001.A.2.CHTS代码:8542.32.00.41
风险等级:5.88Is Samacsys:N
最长访问时间:220 nsJESD-30 代码:R-GDIP-T18
内存密度:4096 bit内存集成电路类型:STANDARD SRAM
内存宽度:1功能数量:1
端口数量:1端子数量:18
字数:4096 words字数代码:4000
工作模式:ASYNCHRONOUS最高工作温度:125 °C
最低工作温度:-55 °C组织:4KX1
输出特性:3-STATE可输出:NO
封装主体材料:CERAMIC, GLASS-SEALED封装形状:RECTANGULAR
封装形式:IN-LINE并行/串行:SERIAL
认证状态:Not Qualified最小待机电流:2 V
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子形式:THROUGH-HOLE端子位置:DUAL
Base Number Matches:1

8102403VA 数据手册

 浏览型号8102403VA的Datasheet PDF文件第2页浏览型号8102403VA的Datasheet PDF文件第3页浏览型号8102403VA的Datasheet PDF文件第4页浏览型号8102403VA的Datasheet PDF文件第5页浏览型号8102403VA的Datasheet PDF文件第6页浏览型号8102403VA的Datasheet PDF文件第7页 
TM  
HM-6504  
March 1997  
4096 x 1 CMOS RAM  
Features  
Description  
• Low Power Standby. . . . . . . . . . . . . . . . . . . 125µW Max The HM-6504 is a 4096 x 1 static CMOS RAM fabricated  
using self-aligned silicon gate technology. The device uti-  
lizes synchronous circuitry to achieve high performance and  
• Low Power Operation . . . . . . . . . . . . . .35mW/MHz Max  
low power operation.  
• Data Retention . . . . . . . . . . . . . . . . . . . . . . . at 2.0V Min  
• TTL Compatible Input/Output  
On-chip latches are provided for addresses, data input and  
data output allowing efficient interfacing with microprocessor  
systems. The data output can be forced to a high impedance  
state for use in expanded memory arrays.  
• Three-State Output  
• Standard JEDEC Pinout  
• Fast Access Time . . . . . . . . . . . . . . . . . 120/200ns Max  
• 18 Lead Package for High Density  
• On-Chip Address Register  
Gated inputs allow lower operating current and also elimi-  
nate the need for pull up or pull down resistors. The  
HM-6504 is a fully static RAM and may be maintained in any  
state for an indefinite period of time.  
• Gated Inputs - No Pull Up or Pull Down Resistors  
Required  
Data retention supply voltage and supply current are guaran-  
teed over temperature.  
Ordering Information  
120ns  
200ns  
300ns  
HM3-6504-9  
HM1-6504-9  
-
TEMP. RANGE  
PACKAGE  
PKG. NO.  
E18.3  
o
o
-
HM1-6504S-9  
24501BVA  
810240IVA  
-
HM3-6504B-9  
-40 C to +85 C  
PDIP  
o
o
HM1-6504B-9  
-40 C to +85 C  
CERDIP  
JAN #  
F18.3  
-
-
-
F18.3  
8102403VA  
-
8102405VA  
HM4-6504-9  
SMD #  
CLCC  
F18.3  
o
o
-40 C to+85 C  
J18.B  
Pinouts  
HM-6504 (PDIP, CERDIP)  
HM-6504 (CLCC)  
TOP VIEW  
TOP VIEW  
PIN  
DESCRIPTION  
Address Input  
Chip Enable  
Write Enable  
Data Input  
A
E
1
2
3
4
5
6
7
8
9
18  
17  
16  
15  
14  
13  
12  
11  
10  
A0  
A1  
A2  
A3  
A4  
A5  
Q
V
CC  
2
1
18 17  
A6  
A7  
A8  
A9  
A10  
A11  
D
16  
A7  
3
4
5
6
7
A2  
A3  
A4  
A5  
Q
W
D
Q
15 A8  
14 A9  
Data Output  
13  
12  
A10  
A11  
W
8
9
10 11  
GND  
E
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.  
FN2994.1  
Copyright © Intersil Americas Inc. 2002. All Rights Reserved  
126  

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