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74VHCT273AMTR PDF预览

74VHCT273AMTR

更新时间: 2024-11-05 05:05:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 触发器
页数 文件大小 规格书
13页 306K
描述
OCTAL D-TYPE FLIP FLOP WITH CLEAR

74VHCT273AMTR 数据手册

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74VHCT273A  
OCTAL D-TYPE FLIP FLOP WITH CLEAR  
HIGH SPEED:  
= 170 MHz (TYP.) at V = 5V  
f
MAX  
CC  
LOW POWER DISSIPATION:  
= 4 µA (MAX.) at T =25°C  
I
CC  
A
COMPATIBLE WITH TTL OUTPUTS:  
= 2V (MIN.), V = 0.8V (MAX)  
V
IH  
IL  
SOP  
TSSOP  
T & R  
POWER DOWN PROTECTION ON INPUTS  
& OUTPUTS  
SYMMETRICAL OUTPUT IMPEDANCE:  
Table 1: Order Codes  
PACKAGE  
|I | = I = 8 mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
PLH  
PHL  
SOP  
74VHCT273AMTR  
74VHCT273ATTR  
OPERATING VOLTAGE RANGE:  
(OPR) = 4.5V to 5.5V  
TSSOP  
V
CC  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 273  
edge of the clock pulse.  
When the CLEAR input is held low, the Q outputs  
are held low independently of the other inputs.  
Power down protection is provided on all inputs  
and outputs and 0 to 7V can be accepted on  
inputs with no regard to the supply voltage. This  
device can be used to interface 5V to 3V since all  
inputs are equipped with TTL threshold.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
IMPROVED LATCH-UP IMMUNITY  
LOW NOISE: V  
= 0.9V (MAX.)  
OLP  
DESCRIPTION  
The 74VHCT273A is an advanced high-speed  
CMOS OCTAL D-TYPE FLIP FLOP WITH CLEAR  
fabricated with sub-micron silicon gate and  
double-layer metal wiring C MOS technology.  
Information signals applied to D inputs are  
transferred to the Q outputs on the positive going  
2
Figure 1: Pin Connection And IEC Logic Symbols  
Rev. 3  
1/13  
December 2004  

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