Datasheet > 74VHCT32D

74VHCT32D

更新时间： 2024-09-17 01:03:51

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
14页	594K
描述
Quad 2-input OR gate

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数据手册

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74VHCT32D 数据手册

74VHC32; 74VHCT32

Quad 2-input OR gate

Rev. 01 — 13 August 2009

Product data sheet

1. General description

The 74VHC32; 74VHCT32 are high-speed Si-gate CMOS devices and are pin compatible

with Low-power Schottky TTL (LSTTL). They are speciﬁed in compliance with JEDEC

standard No. 7-A.

The 74VHC32; 74VHCT32 provide the 2-input OR function.

2. Features

I Balanced propagation delays

I All inputs have Schmitt-trigger actions

I Inputs accept voltages higher than V_CC

I Input levels:

N The 74VHC32 operates with CMOS input level

N The 74VHCT32 operates with TTL input level

I ESD protection:

N HBM JESD22-A114E exceeds 2000 V

N MM JESD22-A115-A exceeds 200 V

N CDM JESD22-C101C exceeds 1000 V

I Multiple package options

I Speciﬁed from −40 °C to +85 °C and from −40 °C to +125 °C

3. Ordering information

Table 1.

Ordering information

Type number

Package

Temperature range Name

Description

Version

74VHC32D

−40 °C to +125 °C

SO14

plastic small outline package; 14 leads;

body width 3.9 mm

SOT108-1

74VHCT32D

74VHC32PW

74VHCT32PW

74VHC32BQ

74VHCT32BQ

TSSOP14

plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

SOT402-1

DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1

thin quad ﬂat package; no leads; 14 terminals;

body 2.5 × 3 × 0.85 mm

12 3 4 5 6 7...14

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74VHCT373AM	STMICROELECTRONICS	获取价格	OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING
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