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74VHCT373A PDF预览

74VHCT373A

更新时间: 2024-11-28 22:56:27
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 输出元件
页数 文件大小 规格书
10页 76K
描述
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING

74VHCT373A 数据手册

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74VHCT373A  
OCTAL D-TYPE LATCH  
WITH 3 STATE OUTPUT NON INVERTING  
HIGH SPEED:tPD =6.4ns (TYP.) atVCC = 5V  
LOW POWER DISSIPATION:  
ICC =4 µA (MAX.) at TA =25 oC  
COMPATIBLEWITH TTL OUTPUTS:  
VIH =2V (MIN), VIL = 0.8V(MAX)  
POWERDOWN PROTECTIONON INPUTS&  
OUTPUTS  
SYMMETRICAL OUTPUT IMPEDANCE:  
|IOH| = IOL = 8 mA (MIN)  
BALANCEDPROPAGATIONDELAYS:  
tPLH tPHL  
M
T
(Micro Package)  
(TSSOPPackage)  
ORDER CODES :  
74VHCT373AM  
74VHCT373AT  
(OE).  
While the LE input is held at a high level, the Q  
outputswill follow the data inputs precisely. When  
the LE is taken low, the Q outputs will be latched  
precisely at the logic level of D input data. While  
the (OE) input is low, the 8 outputs will be in a  
normal logic state (high or low logic level) and  
while high level the outputs will be in a high  
impedance state.  
Power down protection is provided on all inputs  
and outputs and 0 to 7V can be accepted on  
inputs with no regard to the supply voltage. This  
device can be used to interface 5V to 3V.  
OPERATING VOLTAGERANGE:  
VCC (OPR)= 4.5V to 5.5V  
PIN AND FUNCTION COMPATIBLEWITH  
74 SERIES373  
IMPROVED LATCH-UP IMMUNITY  
LOWNOISE:VOLP = 0.9V(Max.)  
DESCRIPTION  
The 74VHCT373A is an advanced high-speed  
CMOS OCTAL D-TYPE LATCH with 3 STATE  
OUTPUT NON INVERTING fabricated with  
sub-micron silicon gate and double-layer metal  
wiring C2MOS technology.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
This 8 bit D-Type latch is controlled by a latch  
enable input (LE) and an output enable input  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
1/10  
November 1999  

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