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74VHCT32AMTR PDF预览

74VHCT32AMTR

更新时间: 2024-11-05 05:05:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 栅极触发器逻辑集成电路光电二极管输入元件
页数 文件大小 规格书
11页 223K
描述
QUAD 2-INPUT OR GATE

74VHCT32AMTR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP14,.25针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.12系列:AHCT/VHCT
JESD-30 代码:R-PDSO-G14JESD-609代码:e4
长度:8.65 mm负载电容(CL):50 pF
逻辑集成电路类型:OR GATE最大I(ol):0.008 A
湿度敏感等级:1功能数量:4
输入次数:2端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP14,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:5 V
Prop。Delay @ Nom-Sup:9 ns传播延迟(tpd):9 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:1.75 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:3.9 mm
Base Number Matches:1

74VHCT32AMTR 数据手册

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74VHCT32A  
QUAD 2-INPUT OR GATE  
HIGH SPEED: t = 5 ns (TYP.) at V = 5V  
PD CC  
LOW POWER DISSIPATION:  
I
= 2 µA (MAX.) at T =25°C  
CC  
A
COMPATIBLE WITH TTL OUTPUTS:  
= 2V (MIN.), V = 0.8V (MAX)  
POWER DOWN PROTECTION ON INPUTS  
& OUTPUTS  
V
IH  
IL  
SOP  
TSSOP  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 8 mA (MIN)  
OH  
OL  
Table 1: Order Codes  
PACKAGE  
BALANCED PROPAGATION DELAYS:  
t
t
PLH  
PHL  
T & R  
OPERATING VOLTAGE RANGE:  
(OPR) = 4.5V to 5.5V  
SOP  
74VHCT32AMTR  
74VHCT32ATTR  
V
CC  
TSSOP  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 32  
IMPROVED LATCH-UP IMMUNITY  
Power down protection is provided on all inputs  
and outputs and 0 to 7V can be accepted on  
inputs with no regard to the supply voltage. This  
device can be used to interface 5V to 3V since all  
inputs are equipped with TTL threshold.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
LOW NOISE: V  
= 0.8V (MAX.)  
OLP  
DESCRIPTION  
The 74VHCT32A is an advanced high-speed  
CMOS QUAD 2-INPUT OR GATE fabricated with  
sub-micron silicon gate and double-layer metal  
2
wiring C MOS technology.  
The internal circuit is composed of 3 stages  
including buffer output, which provides high noise  
immunity and stable output.  
Figure 1: Pin Connection And IEC Logic Symbols  
Rev. 4  
1/11  
December 2004  

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