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74VHCT373A PDF预览

74VHCT373A

更新时间: 2024-11-05 22:56:27
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 锁存器
页数 文件大小 规格书
8页 108K
描述
Octal D-Type Latch with 3-STATE Outputs

74VHCT373A 数据手册

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July 1997  
Revised April 2005  
74VHCT373A  
Octal D-Type Latch with 3-STATE Outputs  
General Description  
Features  
The VHCT373A is an advanced high speed CMOS octal D-  
type latch with 3-STATE output fabricated with silicon gate  
CMOS technology. It achieves the high speed operation  
similar to equivalent Bipolar Schottky TTL while maintain-  
ing the CMOS low power dissipation. This 8-bit D-type  
latch is controlled by a latch enable input (LE) and an out-  
put enable input (OE). The latches appear transparent to  
data when latch enable (LE) is HIGH. When LE is LOW, the  
data that meets the setup time is latched. When the OE  
input is HIGH, the eight outputs are in a high impedance  
state.  
High speed: tPD 7.7 ns (typ) at TA 25 C  
High Noise Immunity: VIH 2.0V, VIL 0.8V  
Power Down Protection is provided on all inputs and  
outputs  
Low Power Dissipation:  
ICC  
4 A (max) @ TA 25 C  
Pin and Function Compatible with 74HCT373  
Protection circuits ensure that 0V to 7V can be applied to  
the input and output (Note 1) pins without regard to the  
supply voltage. This device can be used to interface 3V to  
5V systems and two supply systems such as battery back  
up. This circuit prevents device destruction due to mis-  
matched supply and input voltages.  
Note 1: Outputs in OFF-State.  
Ordering Code:  
Order Number  
74VHCT373AM  
74VHCT373ASJ  
74VHCT373AMTC  
74VHCT373AN  
Package Number  
M20B  
Package Description  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
M20D  
MTC20  
N20A  
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code  
Pb-Free package per JEDEC J-STD-020B.  
Logic Symbol  
Connection Diagram  
IEEE/IEC  
© 2005 Fairchild Semiconductor Corporation  
DS500027  
www.fairchildsemi.com  

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