Datasheet > 74VHC08PW,118

74VHC08PW,118

更新时间： 2024-11-04 15:45:03

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
14页	76K
描述
74VHC(T)08 - Quad 2-input AND gate TSSOP 14-Pin

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中文翻译

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技术参数
数据手册

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74VHC08PW,118 技术参数

Source Url Status Check Date：	2013-06-14 00:00:00	是否Rohs认证：	符合
生命周期：	Transferred	零件包装代码：	TSSOP
包装说明：	4.40 MM, PLASTIC, MO-153, SOT402-1, TSSOP-14	针数：	14
Reach Compliance Code：	compliant	风险等级：	5.77
Is Samacsys：	N	Base Number Matches：	1

74VHC08PW,118 数据手册

74VHC08; 74VHCT08

Quad 2-input AND gate

Rev. 01 — 30 June 2009

Product data sheet

1. General description

The 74VHC08; 74VHCT08 are high-speed Si-gate CMOS devices and are pin compatible

with Low-power Schottky TTL (LSTTL). They are speciﬁed in compliance with JEDEC

standard JESD7-A.

The 74VHC08; 74VHCT08 provide the quad 2-input AND function.

2. Features

I Balanced propagation delays

I All inputs have a Schmitt-trigger action

I Inputs accepts voltages higher than V_CC

I Input levels:

N The 74VHC08 operates with CMOS logic levels

N The 74VHCT08 operates with TTL logic levels

I ESD protection:

N HBM JESD22-A114E exceeds 2000 V

N MM JESD22-A115-A exceeds 200 V

N CDM JESD22-C101C exceeds 1000 V

I Multiple package options

I Speciﬁed from −40 °C to +85 °C and from −40 °C to +125 °C

3. Ordering information

Table 1.

Ordering information

Type number

Package

Temperature range Name

Description

Version

74VHC08D

−40 °C to +125 °C

SO14

plastic small outline package; 14 leads;

body width 3.9 mm

SOT108-1

74VHCT08D

74VHC08PW

74VHCT08PW

74VHC08BQ

74VHCT08BQ

TSSOP14

plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

SOT402-1

SOT762-1

DHVQFN14 plastic dual in-line compatible thermal enhanced very

thin quad ﬂat package; no leads; 14 terminals;

body 2.5 × 3 × 0.85 mm

12 3 4 5 6 7...14

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