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74VHC112SJ PDF预览

74VHC112SJ

更新时间： 2024-09-28 22:56:23
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
7页 73K
描述
Dual J-K Flip-Flops with Preset and Clear

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中文翻译

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74VHC112SJ 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SOP
包装说明：SOP, SOP16,.3针数：16
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.63
Is Samacsys：N系列：AHC/VHC
JESD-30 代码：R-PDSO-G16JESD-609代码：e3
长度：10.1 mm负载电容（CL）：50 pF
逻辑集成电路类型：J-K FLIP-FLOP最大频率@ Nom-Sup：110000000 Hz
最大I（ol）：0.008 A湿度敏感等级：1
位数：2功能数量：2
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C输出极性：COMPLEMENTARY
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP16,.3封装形状：RECTANGULAR
封装形式：SMALL OUTLINE包装方法：RAIL
峰值回流温度（摄氏度）：260电源：2/5.5 V
Prop。Delay @ Nom-Sup：12 ns传播延迟（tpd）：16.5 ns
认证状态：Not Qualified座面最大高度：2.1 mm
子类别：FF/Latches最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
触发器类型：NEGATIVE EDGE宽度：5.3 mm
最小 fmax：135 MHzBase Number Matches：1

74VHC112SJ 数据手册

 浏览型号74VHC112SJ的Datasheet PDF文件第2页浏览型号74VHC112SJ的Datasheet PDF文件第3页浏览型号74VHC112SJ的Datasheet PDF文件第4页浏览型号74VHC112SJ的Datasheet PDF文件第5页浏览型号74VHC112SJ的Datasheet PDF文件第6页浏览型号74VHC112SJ的Datasheet PDF文件第7页 
September 1995  
Revised April 1999  
74VHC112  
Dual J-K Flip-Flops with Preset and Clear  
Simultaneous LOW signals on PR and CLR force both Q  
and Q HIGH.  
General Description  
The VHC112 is an advanced high speed CMOS device  
fabricated with silicon gate CMOS technology. It achieves  
the high-speed operation similar to equivalent Bipolar  
Schottky TTL while maintaining the CMOS low power dissi-  
pation.  
An input protection circuit ensures that 0V to 7V can be  
applied to the input pins without regard to the supply volt-  
age. This device can be used to interface 5V to 3V systems  
and two supply systems such as battery backup. This cir-  
cuit prevents device destruction due to mismatched supply  
and input voltages.  
The VHC112 contains two independent, high-speed JK flip-  
flops with Direct Set and Clear inputs. Synchronous state  
changes are initiated by the falling edge of the clock. Trig-  
gering occurs at a voltage level of the clock and is not  
directly related to transition time. The J and K inputs can  
change when the clock is in either state without affecting  
the flip-flop, provided that they are in the desired state dur-  
ing the recommended setup and hold times relative to the  
falling edge of the clock. The LOW signal on PR or CLR  
prevents clocking and forces Q and Q HIGH, respectively.  
Features  
■ High speed: fMAX = 200 MHz (typ) at VCC = 5.0V  
■ Low power dissipation: ICC = 2 µA (max) at TA = 25°C  
■ High noise immunity: VNIH = VNIL = 28% VCC (min)  
■ Power down protection is provided on all inputs  
■ Pin and function compatible with 74HC112  
Ordering Code:  
Order Number Package Number  
Package Description  
74VHC112M  
74VHC112SJ  
74VHC112MTC  
74VHC112N  
M16A  
M16D  
MTC16  
N16E  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow  
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Pin Descriptions  
Pin Names  
Description  
J1, J2, K1, K2  
CLK1, CLK2  
CLR1, CLR2  
PR1, PR2  
Data Inputs  
Clock Pulse Inputs (Active Falling Edge)  
Direct Clear Inputs (Active LOW)  
Direct Preset Inputs (Active LOW)  
Outputs  
Q1, Q2, Q1, Q2  
© 1999 Fairchild Semiconductor Corporation  
DS012123.prf  
www.fairchildsemi.com  
1234567

中文翻译

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