74VHC08T

更新时间： 2024-09-28 22:56:23

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		输入元件
页数	文件大小	规格书
7页	56K
描述
QUAD 2-INPUT AND GATE

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中文翻译

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数据手册

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74VHC08T 数据手册

74VHC08

QUAD 2-INPUT AND GATE

PRELIMINARY DATA

■

HIGH SPEED:t_PD=4.3ns (TYP.) atV_CC= 5V

LOW POWER DISSIPATION:

_CC=2 µA (MAX.) at T_A=25 ^oC

■

HIGH NOISEIMMUNITY:

_NIH= V_NIL=28% V_CC(MIN.)

■

POWERDOWN PROTECTIONON INPUTS

SYMMETRICAL OUTPUT IMPEDANCE:

|I_OH| = I_OL= 8 mA (MIN)

BALANCEDPROPAGATIONDELAYS:

t_PLHt_PHL

OPERATING VOLTAGERANGE:

V_CC(OPR)= 2V to 5.5V

PIN AND FUNCTION COMPATIBLEWITH

74 SERIES08

(Micro Package)

(TSSOPPackage)

ORDER CODES :

74VHC08M

74VHC08T

■

The internal circuit is composed of 2 stages

including buffer output, which provide high noise

immunity and stable output.

Power down protection is provided on all inputs

and 0 to 7V can be accepted on inputs with no

regard to the supply voltage. This device can be

used to interface5V to 3V.

■

IMPROVED LATCH-UP IMMUNITY

LOWNOISE:V_OLP= 0.8V(Max.)

DESCRIPTION

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

The 74VHC08 is an advanced high-speed CMOS

QUAD 2-INPUT AND GATE fabricated with

sub-micron silicon gate and double-layer metal

wiring C²MOS technology.

PIN CONNECTION AND IEC LOGIC SYMBOLS

1/7

June 1999

12 3 4 5 6 7

中文翻译

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