Datasheet > 74VHC112_07

74VHC112_07

更新时间： 2024-11-16 04:48:03

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		触发器
页数	文件大小	规格书
9页	264K
描述
Dual J-K Flip-Flops with Preset and Clear

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中文翻译

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数据手册

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74VHC112_07 数据手册

May 2007

74VHC112

Dual J-K Flip-Flops with Preset and Clear

Features

General Description

■ High speed: f

= 200MHz (Typ.) at V = 5.0V

The VHC112 is an advanced high speed CMOS device

fabricated with silicon gate CMOS technology. It

achieves the high-speed operation similar to equivalent

Bipolar Schottky TTL while maintaining the CMOS low

power dissipation.

MAX

■ Low power dissipation: I = 2µA (Max.) at T = 25°C

■ High noise immunity: V

= V

= 28% V (Min.)

NIH

NIL CC

■ Power down protection is provided on all inputs

■ Pin and function compatible with 74HC112

The VHC112 contains two independent, high-speed JK

flip-flops with Direct Set and Clear inputs. Synchronous

state changes are initiated by the falling edge of the

clock. Triggering occurs at a voltage level of the clock

and is not directly related to transition time. The J and K

inputs can change when the clock is in either state with-

out affecting the flip-flop, provided that they are in the

desired state during the recommended setup and hold

times relative to the falling edge of the clock. The LOW

signal on PR or CLR prevents clocking and forces Q and

Q HIGH, respectively. Simultaneous LOW signals on PR

and CLR force both Q and Q HIGH.

An input protection circuit ensures that 0V to 7V can be

applied to the input pins without regard to the supply

voltage. This device can be used to interface 5V to 3V

systems and two supply systems such as battery

backup. This circuit prevents device destruction due to

mismatched supply and input voltages.

Ordering Information

Package

Order Number

74VHC112M

Number

Package Description

M16A

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74VHC112SJ

M16D

74VHC112MTC

MTC16

16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the

ordering number.

74VHC112 Rev. 1.2

www.fairchildsemi.com

12 3 4 5 6 7...9

中文翻译

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与74VHC112_07相关器件

型号	品牌	获取价格	描述	数据表
74VHC112M	FAIRCHILD	获取价格	Dual J-K Flip-Flops with Preset and Clear
74VHC112M	TI	获取价格	AHC/VHC SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16,
74VHC112M	ONSEMI	获取价格	带预设和清零功能的双通道J-K触发器
74VHC112MTC	FAIRCHILD	获取价格	Dual J-K Flip-Flops with Preset and Clear
74VHC112MTC	TI	获取价格	AHC/VHC SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16,
74VHC112MTC	ONSEMI	获取价格	带预设和清零功能的双通道J-K触发器
74VHC112MTC_NL	FAIRCHILD	获取价格	J-K Flip-Flop, AHC/VHC Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Outpu
74VHC112MTCX	FAIRCHILD	获取价格	J-K-Type Flip-Flop
74VHC112MTCX	ONSEMI	获取价格	带预设和清零功能的双通道J-K触发器
74VHC112MTCX_NL	FAIRCHILD	获取价格	J-K Flip-Flop, AHC/VHC Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Outpu

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