是否Rohs认证: | 不符合 | 生命周期: | Transferred |
零件包装代码: | SOIC | 包装说明: | SOP, SOP14,.3 |
针数: | 14 | Reach Compliance Code: | unknown |
HTS代码: | 8542.39.00.01 | 风险等级: | 5.41 |
Is Samacsys: | N | 其他特性: | INPUTS CAN BE DRIVEN BY 3V OR 5V COMPONENTS |
系列: | AHC/VHC | JESD-30 代码: | R-PDSO-G14 |
JESD-609代码: | e0 | 长度: | 10.11 mm |
负载电容(CL): | 50 pF | 逻辑集成电路类型: | AND GATE |
最大I(ol): | 0.008 A | 功能数量: | 4 |
输入次数: | 2 | 端子数量: | 14 |
最高工作温度: | 85 °C | 最低工作温度: | -40 °C |
封装主体材料: | PLASTIC/EPOXY | 封装代码: | SOP |
封装等效代码: | SOP14,.3 | 封装形状: | RECTANGULAR |
封装形式: | SMALL OUTLINE | 包装方法: | TAPE AND REEL |
电源: | 2/5.5 V | Prop。Delay @ Nom-Sup: | 9 ns |
传播延迟(tpd): | 9 ns | 认证状态: | Not Qualified |
施密特触发器: | NO | 座面最大高度: | 2.108 mm |
子类别: | Gates | 最大供电电压 (Vsup): | 5.5 V |
最小供电电压 (Vsup): | 2 V | 标称供电电压 (Vsup): | 5 V |
表面贴装: | YES | 技术: | CMOS |
温度等级: | INDUSTRIAL | 端子面层: | Tin/Lead (Sn/Pb) |
端子形式: | GULL WING | 端子节距: | 1.27 mm |
端子位置: | DUAL | 宽度: | 5.3 mm |
Base Number Matches: | 1 |
型号 | 品牌 | 获取价格 | 描述 | 数据表 |
74VHC08SJX_NL | FAIRCHILD |
获取价格 |
AND Gate, CMOS, PDSO14, | |
74VHC08T | STMICROELECTRONICS |
获取价格 |
QUAD 2-INPUT AND GATE | |
74VHC08TTR | STMICROELECTRONICS |
获取价格 |
QUAD 2-INPUT AND GATE | |
74VHC112 | FAIRCHILD |
获取价格 |
Dual J-K Flip-Flops with Preset and Clear | |
74VHC112_07 | FAIRCHILD |
获取价格 |
Dual J-K Flip-Flops with Preset and Clear | |
74VHC112M | FAIRCHILD |
获取价格 |
Dual J-K Flip-Flops with Preset and Clear | |
74VHC112M | TI |
获取价格 |
AHC/VHC SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, | |
74VHC112M | ONSEMI |
获取价格 |
带预设和清零功能的双通道J-K触发器 | |
74VHC112MTC | FAIRCHILD |
获取价格 |
Dual J-K Flip-Flops with Preset and Clear | |
74VHC112MTC | TI |
获取价格 |
AHC/VHC SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, |