Datasheet > 逻辑 > 栅极> 74VHC08SJX_NL

74VHC08SJX_NL

更新时间： 2024-11-04 13:04:59

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		栅
页数	文件大小	规格书
9页	195K
描述
AND Gate, CMOS, PDSO14,

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中文翻译

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技术参数
数据手册

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74VHC08SJX_NL 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
包装说明：	SOP, SOP14,.3	Reach Compliance Code：	compliant
风险等级：	5.84	JESD-30 代码：	R-PDSO-G14
负载电容（CL）：	50 pF	逻辑集成电路类型：	AND GATE
最大I（ol）：	0.008 A	端子数量：	14
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装等效代码：	SOP14,.3	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	包装方法：	TAPE AND REEL
电源：	2/5.5 V	Prop。Delay @ Nom-Sup：	9 ns
认证状态：	Not Qualified	施密特触发器：	NO
子类别：	Gates	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	Base Number Matches：	1

74VHC08SJX_NL 数据手册

May 2007

74VHC08

Quad 2-Input AND Gate

Features

General Description

■ High Speed: t = 4.3ns (Typ.) at T = 25°C

The VHC08 is an advanced high speed CMOS 2 Input

AND Gate fabricated with silicon gate CMOS technol-

ogy. It achieves the high-speed operation similar to

equivalent Bipolar Schottky TTL while maintaining the

CMOS low power dissipation.

■ High noise immunity: V

= V

= 28% V (Min.)

NIH

NIL

■ Power down protection is provided on all inputs

■ Low power dissipation: I = 2µA (Max.) @ T = 25°C

■ Low noise: V

= 0.8V (Max.)

OLP

The internal circuit is composed of 4 stages including

buffer output, which provide high noise immunity and

stable output. An input protection circuit insures that 0V

to 7V can be applied to the input pins without regard to

the supply voltage. This device can be used to interface

5V to 3V systems and two supply systems such as bat-

tery backup. This circuit prevents device destruction due

to mismatched supply and input voltages.

■ Pin and function compatible with 74HC08

Ordering Information

Package

Order Number

Number

Package Description

74VHC08M

M14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"

Narrow

(1)

74VHC08MX_NL

M14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"

Narrow

74VHC08SJ

M14D

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74VHC08MTC

MTC14

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,

4.4mm Wide

(1)

74VHC08MTCX_NL

MTC14

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,

4.4mm Wide

Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the

ordering number. Pb-Free package per JEDEC J-STD-020B.

Note:

1. Device available in Tape and Reel only.

74VHC08 Rev. 1.3

www.fairchildsemi.com

12 3 4 5 6 7...9

中文翻译

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与74VHC08SJX_NL相关器件

型号	品牌	获取价格	描述	数据表
74VHC08T	STMICROELECTRONICS	获取价格	QUAD 2-INPUT AND GATE
74VHC08TTR	STMICROELECTRONICS	获取价格	QUAD 2-INPUT AND GATE
74VHC112	FAIRCHILD	获取价格	Dual J-K Flip-Flops with Preset and Clear
74VHC112_07	FAIRCHILD	获取价格	Dual J-K Flip-Flops with Preset and Clear
74VHC112M	FAIRCHILD	获取价格	Dual J-K Flip-Flops with Preset and Clear
74VHC112M	TI	获取价格	AHC/VHC SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16,
74VHC112M	ONSEMI	获取价格	带预设和清零功能的双通道J-K触发器
74VHC112MTC	FAIRCHILD	获取价格	Dual J-K Flip-Flops with Preset and Clear
74VHC112MTC	TI	获取价格	AHC/VHC SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16,
74VHC112MTC	ONSEMI	获取价格	带预设和清零功能的双通道J-K触发器

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