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74VCX16601MTD PDF预览

74VCX16601MTD

更新时间: 2024-09-15 22:45:59
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器触发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
11页 158K
描述
Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs

74VCX16601MTD 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:6.10 MM, MO-153, TSSOP-56
针数:56Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.71
Is Samacsys:N其他特性:WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
控制类型:INDEPENDENT CONTROL计数方向:BIDIRECTIONAL
系列:ALVC/VCX/AJESD-30 代码:R-PDSO-G56
JESD-609代码:e3长度:14 mm
负载电容(CL):30 pF逻辑集成电路类型:REGISTERED BUS TRANSCEIVER
最大I(ol):0.018 A湿度敏感等级:2
位数:18功能数量:1
端口数量:2端子数量:56
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP56,.3,20封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:RAIL
峰值回流温度(摄氏度):260电源:3.3 V
Prop。Delay @ Nom-Sup:2.9 ns传播延迟(tpd):17.6 ns
认证状态:Not Qualified座面最大高度:1.1 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):1.4 V标称供电电压 (Vsup):1.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
翻译:N/A触发器类型:POSITIVE EDGE
宽度:6.1 mmBase Number Matches:1

74VCX16601MTD 数据手册

 浏览型号74VCX16601MTD的Datasheet PDF文件第2页浏览型号74VCX16601MTD的Datasheet PDF文件第3页浏览型号74VCX16601MTD的Datasheet PDF文件第4页浏览型号74VCX16601MTD的Datasheet PDF文件第5页浏览型号74VCX16601MTD的Datasheet PDF文件第6页浏览型号74VCX16601MTD的Datasheet PDF文件第7页 
March 1998  
Revised October 2004  
74VCX16601  
Low Voltage 18-Bit Universal Bus Transceivers  
with 3.6V Tolerant Inputs and Outputs  
General Description  
The VCX16601 is an 18-bit universal bus transceiver which  
combines D-type latches and D-type flip-flops to allow data  
flow in transparent, latched, and clocked modes.  
Features  
1.4V to 3.6V VCC supply operation  
3.6V tolerant inputs and outputs  
tPD (A to B, B to A)  
Data flow in each direction is controlled by output-enable  
(OEAB and OEBA), latch-enable (LEAB and LEBA), and  
clock (CLKAB and CLKBA) inputs. The clock can be con-  
trolled by the clock-enable (CLKENAB and CLKENBA)  
inputs. For A-to-B data flow, the device operates in the  
transparent mode when LEAB is HIGH. When LEAB is  
LOW, the A data is latched if CLKAB is held at a HIGH-to-  
LOW logic level. If LEAB is LOW, the A bus data is stored  
in the latch/flip-flop on the LOW-to-HIGH transition of  
CLKAB. When OEAB is LOW, the outputs are active. When  
OEAB is HIGH, the outputs are in the high-impedance  
state.  
2.9 ns max for 3.0V to 3.6V VCC  
Power-down high impedance inputs and outputs  
Supports live insertion/withdrawal (Note 1)  
Static Drive (IOH/IOL  
)
±24 mA @ 3.0V VCC  
Uses patented noise/EMI reduction circuitry  
Latchup performance exceeds 300 mA  
ESD performance:  
Human body model > 2000V  
Data flow for B to A is similar to that of A to B but uses  
OEBA, LEBA, CLKBA and CLKENBA.  
Machine model >200V  
Also packaged in plastic Fine-Pitch Ball Grid Array  
The VCX16601 is designed for low voltage (1.4V to 3.6V)  
VCC applications with I/O capability up to 3.6V.  
(FBGA) (Preliminary)  
Note 1: To ensure the high-impedance state during power up or power  
down, OE should be tied to VCC through a pull-up resistor; the minimum  
The VCX16601 is fabricated with an advanced CMOS  
technology to achieve high speed operation while maintain-  
ing low CMOS power dissipation.  
value of the resistor is determined by the current-sourcing capability of the  
driver.  
Ordering Code:  
Order Number Package Number  
Package Description  
74VCX16601GX  
(Note 2)  
BGA54A  
(Preliminary)  
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide  
[TAPE and REEL]  
74VCX16601MTD  
(Note 3)  
MTD56  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
Note 2: BGA package available in Tape and Reel only.  
Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
© 2004 Fairchild Semiconductor Corporation  
DS500126  
www.fairchildsemi.com  

74VCX16601MTD 替代型号

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