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74LVTH16240MEAX_NL PDF预览

74LVTH16240MEAX_NL

更新时间： 2024-09-15 20:44:15
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 驱动信息通信管理光电二极管逻辑集成电路
页数 文件大小 规格书
6页 105K
描述
Bus Driver, LVT Series, 4-Func, 4-Bit, Inverted Output, BICMOS, PDSO48, 0.300 INCH, LEAD FREE, MO-118, SSOP-48

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74LVTH16240MEAX_NL 技术参数

生命周期：Obsolete零件包装代码：SSOP
包装说明：SSOP,针数：48
Reach Compliance Code：unknown风险等级：5.76
系列：LVTJESD-30 代码：R-PDSO-G48
JESD-609代码：e3长度：15.875 mm
逻辑集成电路类型：BUS DRIVER位数：4
功能数量：4端口数量：2
端子数量：48最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：INVERTED封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH传播延迟（tpd）：4.2 ns
认证状态：Not Qualified座面最大高度：2.74 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：BICMOS温度等级：INDUSTRIAL
端子面层：MATTE TIN端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
宽度：7.5 mmBase Number Matches：1

74LVTH16240MEAX_NL 数据手册

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March 1999  
Revised June 2005  
74LVT16240 • 74LVTH16240  
Low Voltage 16-Bit Inverting Buffer/Line Driver  
with 3-STATE Outputs  
General Description  
Features  
■ Input and output interface capability to systems at  
The LVT16240 and LVTH16240 contain sixteen inverting  
buffers with 3-STATE outputs designed to be employed as  
a memory and address driver, clock driver, or bus-oriented  
transmitter/receiver. The device is nibble controlled.  
5V VCC  
■ Bushold data inputs eliminate the need for external  
pull-up resistors to hold unused inputs (74LVTH16240),  
also available without bushold feature (74LVT16240)  
Individual 3-STATE control inputs can be shorted together  
for 8-bit or 16-bit operation.  
■ Live insertion/extraction permitted  
The LVTH16240 data inputs include bushold, eliminating  
the need for external pull-up resistors to hold unused  
inputs.  
■ Power Up/Down high impedance provides glitch-free  
bus loading  
■ Outputs source/sink 32 mA/ 64 mA  
■ Functionally compatible with the 74 series 16240  
■ Latch-up performance exceeds 500 mA  
■ ESD performance:  
These buffers and line drivers are designed for low-voltage  
(3.3V) VCC applications, but with the capability to provide a  
TTL interface to a 5V environment. The LVT16240 and  
LVTH16240 are fabricated with an advanced BiCMOS  
technology to achieve high speed operation similar to 5V  
ABT while maintaining a low power dissipation.  
Human-body model 2000V  
Machine model 200V  
Charged-device model 1000V  
Ordering Code:  
Package  
Order Number  
Package Description  
Number  
74LVT16240MEA  
74LVT16240MTD  
74LVTH16240MEA  
74LVTH16240MTD  
MS48A  
MTD48  
MS48A  
MTD48  
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbol  
© 2005 Fairchild Semiconductor Corporation  
DS012025  
www.fairchildsemi.com  
123456

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