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74LVTH16244 PDF预览

74LVTH16244

更新时间: 2024-11-05 05:05:51
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 信息通信管理高压
页数 文件大小 规格书
13页 189K
描述
LOW VOLTAGE BICMOS 16 BIT BUS BUFFER WITH BUS HOLD AND POWER UP 3-STATE

74LVTH16244 数据手册

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74LVTH16244  
LOW VOLTAGE BICMOS 16 BIT BUS BUFFER  
WITH BUS HOLD AND POWER UP 3-STATE  
HIGH SPEED:  
= 3.2ns (MAX.) at T = 85°C V = 3.0V  
LOW POWER DISSIPATION HIGH LEVEL  
t
PD  
A
CC  
OUTPUT: I = 190µA (MAX.) at T = 85°C  
CC  
A
OUTPUT IMPEDANCE:  
|I | = 32mA, I = 64mA (MIN at V = 3.0V)  
OH  
OL  
CC  
|I | = 8mA, I = 24mA (MIN at V = 2.7V)  
OH  
OL  
CC  
TSSOP  
TFBGA  
BALANCED PROPAGATION DELAYS:  
t
t
PLH  
PHL  
POWER DOWN PROTECTION ON INPUTS  
AND OUTPUTS  
COMPATIBLE WITH TTL OUTPUTS:  
ORDER CODES  
PACKAGE  
T & R  
TSSOP48  
TFBGA54  
74LVTH16244TTR  
74LVTH16244LBR  
V
= 2V (MIN),V = 0.8V(MAX) at  
IH  
IL  
V
= 2.7 to 3.6V  
CC  
POWER-UP/DOWN 3-STATE: I  
= 100µA  
OZPU  
LOGIC DIAGRAM  
MAX at V = 0V to 1.5V, V = 1.5V to 0V, T  
CC  
CC  
A
= 85°C  
BUS HOLD PROVIDED ON DATA INPUTS  
OPERATING VOLTAGE RANGE:  
V
(OPR) = 2.7V to 3.6V  
CC  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES H16244  
LATCH-UP PERFORMANCE EXCEEDS  
500mA (JESD 17)  
DESCRIPTION  
The 74LVTH16244 is a low voltage BiCMOS 16  
BIT BUS BUFFER (NON-INVERTED) fabricated  
with sub-micron silicon gate and five-layer metal  
wiring BiCMOS technology. It is ideal and full  
specified for hot-insertion and high speed 3.3V ap-  
plications; the power-up/down 3-state circuitry  
places the outputs in the high impedance state  
during power-up/down, which prevents driver con-  
flict. This function is guaranteed when V  
is be-  
CC  
tween 0 and 1.5V. It can be interfaced to 3.3V sig-  
nal environment for both inputs and outputs. Any  
nG output control governs four BUS BUFFERS.  
Output Enable input (nG) tied together gives full  
16-bit operation. When nG is LOW, the outputs  
are on. When nG is HIGH, the output are in high  
impedance state effectively isolated. Bus hold on  
data inputs is provided in order to eliminate the  
need for external pull-up or pull-down resistors.  
All inputs and outputs are equipped with protec-  
tion circuits against static discharge, giving them  
ESD immunity and transient excess voltage.  
February 2004  
1/13  

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