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74LVC74APW,112 PDF预览

74LVC74APW,112

更新时间: 2024-11-23 14:50:27
品牌 Logo 应用领域
恩智浦 - NXP 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
19页 139K
描述
74LVC74A - Dual D-type flip-flop with set and reset; positive-edge trigger TSSOP 14-Pin

74LVC74APW,112 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:TSSOP包装说明:TSSOP, TSSOP14,.25
针数:14Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.18
系列:LVC/LCX/ZJESD-30 代码:R-PDSO-G14
JESD-609代码:e4长度:5 mm
负载电容(CL):50 pF逻辑集成电路类型:D FLIP-FLOP
最大频率@ Nom-Sup:120000000 Hz最大I(ol):0.024 A
湿度敏感等级:1位数:1
功能数量:2端子数量:14
最高工作温度:125 °C最低工作温度:-40 °C
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TUBE峰值回流温度(摄氏度):260
电源:3.3 VProp。Delay @ Nom-Sup:6.5 ns
传播延迟(tpd):7.5 ns认证状态:Not Qualified
座面最大高度:1.1 mm子类别:FF/Latches
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):1.2 V
标称供电电压 (Vsup):2.7 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:NICKEL PALLADIUM GOLD端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30触发器类型:POSITIVE EDGE
宽度:4.4 mm最小 fmax:120 MHz
Base Number Matches:1

74LVC74APW,112 数据手册

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74LVC74A  
Dual D-type flip-flop with set and reset; positive-edge trigger  
Rev. 7 — 20 November 2012  
Product data sheet  
1. General description  
The 74LVC74A is a dual edge triggered D-type flip-flop with individual data (nD) inputs,  
clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs.  
The set and reset are asynchronous active LOW inputs and operate independently of the  
clock input. Information on the data input is transferred to the nQ output on the  
LOW-to-HIGH transition of the clock pulse. The nD inputs must be stable one set-up time  
prior to the LOW-to-HIGH clock transition, for predictable operation.  
Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and  
fall times.  
2. Features and benefits  
5 V tolerant inputs for interlacing with 5 V logic  
Wide supply voltage range from 1.2 V to 3.6 V  
CMOS low power consumption  
Direct interface with TTL levels  
Complies with JEDEC standard:  
JESD8-7A (1.65 V to 1.95 V)  
JESD8-5A (2.3 V to 2.7 V)  
JESD8-C/JESD36 (2.7 V to 3.6 V)  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-B exceeds 200 V  
CDM JESD22-C101E exceeds 1000 V  
Specified from 40 C to +85 C and 40 C to +125 C  
 
 

74LVC74APW,112 替代型号

型号 品牌 替代类型 描述 数据表
74LVC74APW,118 NXP

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74LVC74A - Dual D-type flip-flop with set and reset; positive-edge trigger TSSOP 14-Pin
74LVC74APW-T NXP

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IC LVC/LCX/Z SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO1
74LVC74APW NXP

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Dual D-type flip-flop with set and reset; positive-edge trigger

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