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74LVC16374ADGVRG4 PDF预览

74LVC16374ADGVRG4

更新时间： 2024-09-15 02:58:15
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德州仪器 - TI /
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描述
16-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputs

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74LVC16374ADGVRG4 数据手册

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SN74LVC16374A  
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCAS728A–OCTOBER 2003–REVISED OCTOBER 2005  
FEATURES  
DGG, DGV, OR DL PACKAGE  
(TOP VIEW)  
•
•
•
•
•
Member of the Texas Instruments Widebus™  
Family  
1
48 1CLK  
47 1D1  
1OE  
1Q1  
1Q2  
GND  
1Q3  
1Q4  
Typical VOLP (Output Ground Bounce) <0.8 V  
at VCC = 3.3 V, TA = 25°C  
2
46  
3
1D2  
Typical VOHV (Output VOH Undershoot) >2 V at  
VCC = 3.3 V, TA = 25°C  
4
45 GND  
44 1D3  
43 1D4  
5
Ioff Supports Partial-Power-Down Mode  
Operation  
6
7
42  
41  
40  
39  
V
CC  
V
CC  
Supports Mixed-Mode Signal Operation on All  
Ports (5-V Input and Output Voltages With  
8
1D5  
1D6  
GND  
1Q5  
1Q6  
GND  
1Q7  
1Q8  
2Q1  
2Q2  
GND  
2Q3  
2Q4  
9
3.3-V VCC  
)
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
•
•
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
38 1D7  
37 1D8  
36 2D1  
ESD Protection Exceeds JESD 22  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
2D2  
GND  
2D3  
2D4  
– 2000-V Human-Body Model (A114-A)  
– 1000-V Charged-Device Model (C101)  
DESCRIPTION/ORDERING INFORMATION  
V
CC  
V
CC  
This 16-bit edge-triggered D-type flip-flop is designed  
for 1.65-V to 3.6-V VCC operation.  
2D5  
2D6  
GND  
2D7  
2D8  
2CLK  
2Q5  
2Q6  
GND  
2Q7  
2Q8  
2OE  
The SN74LVC16374A is particularly suitable for  
implementing buffer registers, I/O ports, bidirectional  
bus drivers, and working registers. The device can be  
used as two 8-bit flip-flops or one 16-bit flip-flop. On  
the positive transition of the clock (CLK) input, the Q  
outputs of the flip-flop take on the logic levels set up  
at the data (D) inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or  
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the  
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines  
without interface or pullup components.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
SN74LVC16374AGRDR  
SN74LVC16374AZRDR  
SN74LVC16374ADL  
TOP-SIDE MARKING  
FBGA – GRD  
Tape and reel  
LD374A  
FBGA – ZRD (Pb-free)  
Tube  
SSOP – DL  
LVC16374A  
LVC16374A  
LD374A  
Tape and reel  
SN74LVC16374ADLR  
SN74LVC16374ADGGR  
74LVC16374ADGGRG4  
SN74LVC16374ADGVR  
74LVC16374ADGVRE4  
SN74LVC16374AGQLR  
SN74LVC16374AZQLR  
–40°C to 85°C  
TSSOP – DGG  
TVSOP – DGV  
Tape and reel  
Tape and reel  
Tape and reel  
VFBGA – GQL  
LD374A  
VFBGA – ZQL (Pb-free)  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2003–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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74LVC16374ADGVRG4 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVC16374ADGVR TI

类似代替

 16 BIT EDGE TRIGGERED D TYPE FLIP FLOP WITH 3 STATE OUTPUTS

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