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74LVC163PW,112 PDF预览

74LVC163PW,112

更新时间： 2024-11-05 15:26:39
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恩智浦 - NXP 光电二极管输出元件逻辑集成电路触发器
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描述
74LVC163 - Presettable synchronous 4-bit binary counter; synchronous reset TSSOP 16-Pin

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74LVC163PW,112 技术参数

是否Rohs认证： 符合生命周期：Transferred
零件包装代码：TSSOP包装说明：TSSOP, TSSOP16,.25
针数：16Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.18
其他特性：TCO OUTPUT计数方向：UP
系列：LVC/LCX/ZJESD-30 代码：R-PDSO-G16
JESD-609代码：e4长度：5 mm
负载电容（CL）：50 pF负载/预设输入：YES
逻辑集成电路类型：BINARY COUNTER最大频率@ Nom-Sup：120000000 Hz
最大I（ol）：0.024 A工作模式：SYNCHRONOUS
湿度敏感等级：1位数：4
功能数量：1端子数量：16
最高工作温度：125 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP16,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法：TUBE
峰值回流温度（摄氏度）：260电源：3.3 V
传播延迟（tpd）：9.5 ns认证状态：Not Qualified
座面最大高度：1.1 mm子类别：Counters
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：1.2 V
标称供电电压 (Vsup)：2.7 V表面贴装：YES
技术：CMOS温度等级：AUTOMOTIVE
端子面层：NICKEL PALLADIUM GOLD端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30触发器类型：POSITIVE EDGE
宽度：4.4 mm最小 fmax：150 MHz
Base Number Matches：1

74LVC163PW,112 数据手册

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74LVC163  
Presettable synchronous 4-bit binary counter; synchronous  
reset  
Rev. 6 — 20 November 2012  
Product data sheet  
1. General description  
The 74LVC163 is a synchronous presettable binary counter which features an internal  
look-ahead carry and can be used for high-speed counting. Synchronous operation is  
provided by having all flip-flops clocked simultaneously on the positive-going edge of the  
clock (pin CP). The outputs (pins Q0 to Q3) of the counters may be preset to a HIGH-level  
or LOW-level. A LOW-level at the parallel enable input (pin PE) disables the counting  
action and causes the data at the data inputs (pins D0 to D3) to be loaded into the counter  
on the positive-going edge of the clock (provided that the set-up and hold time  
requirements for PE are met). Preset takes place regardless of the levels at count enable  
inputs (pin CEP and CET). A LOW-level at the master reset input (pin MR) sets all four  
outputs of the flip-flops (pins Q0 to Q3) to LOW-level after the next positive-going  
transition on the clock input (pin CP) (provided that the set-up and hold time requirements  
for PE are met). This action occurs regardless of the levels at input pins PE, CET and  
CEP. This synchronous reset feature enables the designer to modify the maximum count  
with only one external NAND gate.  
The look-ahead carry simplifies serial cascading of the counters. Both count enable inputs  
(pin CEP and CET) must be HIGH in count. The CET input is fed forward to enable the  
terminal count output (pin TC). The TC output thus enabled will produce a HIGH output  
pulse of a duration approximately equal to a HIGH-level output of Q0. This pulse can be  
used to enable the next cascaded stage.  
The maximum clock frequency for the cascaded counters is determined by tPHL  
(propagation delay CP to TC) and tsu (set-up time CEP to CP) according to the formula:  
1
.
fmax  
=
-----------------------------------  
t
PHLmax+ tsu  
2. Features and benefits  
Wide supply voltage range from 1.2 V to 3.6 V  
Inputs accept voltages up to 5.5 V  
CMOS low power consumption  
Direct interface with TTL levels  
Synchronous reset  
Synchronous counting and loading  
Two count enable inputs for n-bit cascading  
Positive edge-triggered clock  
Complies with JEDEC standard:  
JESD8-7A (1.65 V to 1.95 V)  
JESD8-5A (2.3 V to 2.7 V)  
 
 
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74LVC163PW,112 替代型号

型号 品牌 替代类型 描述 数据表
74LVC161PW,118 NXP

完全替代

 74LVC161 - Presettable synchronous 4-bit binary counter; asynchronous reset TSSOP 16-Pin

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