Datasheet > 74LVC16374A-Q100

74LVC16374A-Q100

更新时间： 2024-09-15 01:07:47

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
14页	230K
描述
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state

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74LVC16374A-Q100 数据手册

74LVC16374A-Q100;

74LVCH16374A-Q100

16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state

Rev. 2 — 20 November 2018

Product data sheet

1. General description

The 74LVC16374A-Q100 and 74LVCH16374A-Q100 are 16-bit edge-triggered flip-flops featuring

separate D-type inputs with bus hold (74LVCH16374A-Q100 only) for each flip-flop and 3-state

outputs for bus-oriented applications. It consists of two sections of eight positive edge-triggered flip-

flops. A clock input (nCP) and an output enable (nOE) are provided for each octal.

The flip-flops store the state of their individual D-inputs that meet the set-up and hold time

requirements on the LOW-to-HIGH clock (CP) transition.

When pin nOE is LOW, the contents of the flip-flops are available at the outputs. When pin nOE is

HIGH, the outputs go to the high-impedance OFF-state. Operation of input nOE does not affect the

state of the flip-flops.

Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to

the outputs. These features allow the use of these devices in mixed 3.3 V and 5 V applications.

Bus hold on data inputs eliminates the need for external pull-up resistors to hold unused inputs.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100

(Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

•

Automotive product qualification in accordance with AEC-Q100 (Grade 1)

Specified from -40 °C to +85 °C and from -40 °C to +125 °C

•

5 V tolerant inputs/outputs for interfacing with 5 V logic

Wide supply voltage range from 1.2 V to 3.6 V

CMOS low power consumption

Multibyte flow-through standard pinout architecture

Low inductance multiple supply pins for minimum noise and ground bounce

Direct interface with TTL levels

All data inputs have bus hold (74LVCH16374A-Q100 only)

High-impedance outputs when V_CC= 0 V

Complies with JEDEC standard:

•

JESD8-7A (1.65 V to 1.95 V)

JESD8-5A (2.3 V to 2.7 V)

JESD8-C/JESD36 (2.7 V to 3.6 V)

•

ESD protection:

•

MIL-STD-883, method 3015 exceeds 2000 V

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-A exceeds 200 V (C = 200 pF; R = 0 Ω)

12 3 4 5 6 7...14

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与74LVC16374A-Q100相关器件

型号	品牌	获取价格	描述	数据表
74LVC16374PW-T	NXP	获取价格	IC LVC/LCX/Z SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48, Bus Driver/Transceiver
74LVC163BQ	NEXPERIA	获取价格	Presettable synchronous 4-bit binary counter; synchronous resetProduction
74LVC163D	NXP	获取价格	Presettable synchronous 4-bit binary counter; synchronous reset
74LVC163D	NEXPERIA	获取价格	Presettable synchronous 4-bit binary counter; synchronous resetProduction
74LVC163D,112	NXP	获取价格	74LVC163 - Presettable synchronous 4-bit binary counter; synchronous reset SOP 16-Pin
74LVC163D,118	NXP	获取价格	74LVC163 - Presettable synchronous 4-bit binary counter; synchronous reset SOP 16-Pin
74LVC163DB	NXP	获取价格	Presettable synchronous 4-bit binary counter; synchronous reset
74LVC163DB,112	NXP	获取价格	74LVC163 - Presettable synchronous 4-bit binary counter; synchronous reset SSOP1 16-Pin
74LVC163DB,118	NXP	获取价格	74LVC163 - Presettable synchronous 4-bit binary counter; synchronous reset SSOP1 16-Pin
74LVC163DB-T	ETC	获取价格	Synchronous Up Counter

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